Writing Fast State Machines using SystemVerilog

Hello, I came across this article that commented on using State Machines with One-Hot encoding.

http://www.verilogpro.com/systemveri...state-machine/

The article state,

"According to Cliff Cummings’ 2003 paper, this coding style yields poor performance because the Design Compiler infers a full 4-bit comparison against the state vector, in effect defeating the speed advantage of a one-hot state machine."

Can anyone recommend the best method to achieve speed?

Thanks,
Joe