register's initial value during reset state

Hi,

Is it customary and synthesizable to enter the initial value that different from 'zero' during reset state?

for instance:
"
if reset = '1' then
reg <= "01";
reg_1 <= x"11";
elsif(-----) then
~
end if;
"

reg - internal signal inside the code
reg_1 - out put signal(FPGA envelop)

Tnx