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downloding web server labraries

Hi, i'd like to try srver web applications offered by Altera ,while searching i find that i should have embedded libraries for (HTTP,FTP,TCP/IP ,...) web server .I tried to download it but i didn't...

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Edge detection VHDL (what's the best solution)

Hello everybody Well for Edge detection we always use C language because it's much easier to code the algorithm !! What do you think is the best solution that can be coded in VHDL for edge detection or...

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converting DE2_NET to use web server

Can i use the SOPC generated from the DE2_NET demo to create a web server using the template? I tried it but i got errors..... Attached Images ERROR_DE2_NET.JPG (109.8 KB)

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Verilog modules

Hi all, I have recently purchased a DE1 which I have been playing round with and attempting to learn Verilog. I have a question in regards to modules. Currently I am using the DE1 to emulate a gameboy...

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vhdl code for 8 bit simple cpu

hey everyone i need a simple 8 bit cpu code which does alu and shifter opertions....... i am working with DE2-115 board....... i was coding it myself by taking reference dy Douglas L. Perry but it did...

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register's initial value during reset state

Hi, Is it customary and synthesizable to enter the initial value that different from 'zero' during reset state? for instance: " if reset = '1' then reg <= "01"; reg_1 <= x"11"; elsif(-----) then...

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vhdl code for 8 bit simple cpu

hey friends i need a simple 8 bit cpu vhdl code with alu and shifter operation ......i m working with de2....plz help me

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altlvds_rx

I am trying to simulate an Arria V altlvds_rx mega-function using modelsim10.0c starter edition. From some reason in the simulation the rx_out port is always '0' and the rx_outclock port is always 'X'....

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altlvds_rx

I am trying to simulate an Arria V altlvds_rx mega-function using modelsim10.0c starter edition. From some reason in the simulation the rx_out port is always '0' and the rx_outclock port is always 'X'....

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function syntax error for matrix multiplication

respected guiders ... i have written a vhdl code for matrix multiplication of two matrices. but when i compile the code, i am getting a function syntax error. can anyone help me out of this please......

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Over heating of ARRIA V

We have a problem of Arria V overheating. We calculated the heat with the " power play early power estimator". The results were: Junction Temp, TJ (oC) = 80c qJA Junction-Ambient = 9.1c Maximum Allowed...

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pll does not simulate

trying to run a simulation with Altera modelsim 10.0c starter edition, and recieve the following: Warning: (vsim-3473) Component instance "pll_rx_inst : pll_rx_0002" is not bound

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MTD issue on the DE2-115

Hi Everyone, Did anyone successfully running the uClinux and mount the mtd0 (8MB Flash memory) on the DE2-115? I tried to do the "flash_erase /dev/mtd0 0 3" and got error return message "No such...

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Time constraint and IP core

Hello, There're some things I'm confusing about time constraint or my design. Is there any time constraint, which is embedded to code of the IP core to constraint logics inside it? Because some IP...

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Fmax and Restricted Max

Hello, In the Time Quest, the Fmax for my design is 303 MHz , but the Restricted Fmax is 250 MHz with a Note that says 'limit due to minimum period restriction (max I/O toggle rate)' . The clock...

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Producing tone with Audio Codec on NIOS II?

Hey everyone, I'm just learning how to use the Audio CODEC on NIOS II with the DE2 board. I wrote the following assembly code to generate a square wave and use it to produce an output tone: .equ...

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UART and RS485: how to control transmit enable on RS485

Hi Forum I am pretty new working with FPGAs. I am using the Altera UART IP core which is connected to a RS485 transmitter. The RS485 transmitter have a receive-enable pin and a transmit enable pin....

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library auk_dspip_lib not found

Hi , When trying to simulate a Altera generated ip FIR filter i got this error message "library auk_dspip_lib not found" ? How do i remove this bug ?? Regards ,

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files reordered when opening quartus project

Hello, I have been busy with making a project last friday, today I wanted to work on that. But all I got was a quartus screen and it send me to this page:...

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Request for an example of setting Mac address in Mac Control Interface

After find the example of Avalon MM, i do not know how to apply to Mac Control Interface how to set address of register of mac address to address[7:0] ? any example about this setting?

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