Hi,
I've been learning VHDL this semester and am trying to build a program that can take two input signals and cross correlate them. I've tried to implement a brute force summation algorithm, but it seems like the compiler just ignores most of what I tried to do. I think this means I'm writing un-synthesizable code, but I haven't yet figured out how to know if what I write can be created in hardware or not.
Here's one of my tries so far. Ultimately I'd like to make the inputs vectors of unsigned or standard logic, but for now I just want it to work with anything.
I've been learning VHDL this semester and am trying to build a program that can take two input signals and cross correlate them. I've tried to implement a brute force summation algorithm, but it seems like the compiler just ignores most of what I tried to do. I think this means I'm writing un-synthesizable code, but I haven't yet figured out how to know if what I write can be created in hardware or not.
Here's one of my tries so far. Ultimately I'd like to make the inputs vectors of unsigned or standard logic, but for now I just want it to work with anything.
Code:
PACKAGE dataTypes IS
TYPE inputVector IS ARRAY (NATURAL RANGE <>) OF INTEGER;
TYPE outputVector IS ARRAY (NATURAL RANGE <>) OF INTEGER;
END PACKAGE dataTypes;
---------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE work.dataTypes.all;
---------------------------------------------------------------------
ENTITY xcorr is
GENERIC
(
Nrcv: NATURAL := 16;
Nknwn: NATURAL := 4
);
PORT
(
rcvSig: IN inputVector(1 TO Nrcv);
knwnSig: IN inputVector(1 TO Nknwn);
clk: IN STD_LOGIC;
corrSig: OUT outputVector(1 TO (Nrcv+Nknwn-1))
);
END ENTITY;
---------------------------------------------------------------------
ARCHITECTURE circuit OF xcorr IS
CONSTANT zeroKnwnSig: inputVector(1 TO Nknwn) := (OTHERS => 0);
CONSTANT padRcvSig: inputVector(1 TO (Nrcv + 2*Nknwn)) := (zeroKnwnSig & rcvSig & zeroKnwnSig);
BEGIN
compute_output: PROCESS (clk)
VARIABLE tempCorrSig: outputVector(1 TO (Nrcv+Nknwn-1)) := (OTHERS => 0);
VARIABLE sum: INTEGER;
BEGIN
IF clk'EVENT AND clk = '1' THEN
FOR i IN 1 TO Nrcv LOOP
sum := 0;
FOR j IN 1 TO Nknwn LOOP
sum := sum + knwnSig(j) * padRcvSig(i+j);
END LOOP;
tempCorrSig(i) := sum;
END LOOP;
--ELSE
--NULL;
END IF;
corrSig <= tempCorrSig;
END PROCESS;
END ARCHITECTURE;