Qsys Keep generating Verilog files when I want VHDL
How do I get QSYS to stop generating Verilog and start generating VHDL code for my system module. Under the Generation tab I keep selecting VHDL but Somehow it keeps spitting out verilog. Grr.. Thanks
View Articleblock ram area equivalent in logic elements , Cyclone iv
Hi, I have several designs synthesized on cyclone iv fpga and all of them use only 2 resources : Logic elements and Block Rams (M9k). I want to compare the area consumption of the designs , but since...
View ArticleError: Selected device has 105 RAM location
Hello when I was in the process of compiling my program I got this error Code: Error: Selected device has 105 RAM location(s) of type M4K. However, the current design needs more than 105 to...
View ArticleHelp with cross correlation
Hi, I've been learning VHDL this semester and am trying to build a program that can take two input signals and cross correlate them. I've tried to implement a brute force summation algorithm, but it...
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This circuit to Verilog model.. Is it possible?
My background is on pure Digital design on verilog coding. My friend ask me if it is possible to model the bellow circuit into verilog and use the verilog codes to DE0-NANO FPGA board. If it is...
View ArticleBuffer port in Quartus schematic
Hello all, Does anybody know how to put a buffer symbol as a buffer port in Quartus schematic? In VHDL, I can simply use folloing line to declare a buffer port in Entity part. aluout: buffer...
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Sopc design - Urgent Help
I am just trying to display an image through VGA....port in DE2-115 board...i have tried many sopc design....but get an error while programming the flash memory....i have attached the sopc design with...
View Articlewhich part of data in ethernet frame should be passed to CRC generator?
after pass payload to CRC generator, wireshark do not receive any ethernet frame i guess wrong, i do not know where to check, i am afraid that ethernet port in PC side drop the frame from FPGA when CRC...
View ArticleHow to implement the image processing algorithm in DE2-115 board using NIOS-II
i have an DE2-115 board.now i want to write a image (input) and read a image(output ) in DE2-115 board using NIOS-II processor.what are steps i am going to follow? Regards, Karthikeyan.P
View ArticleCan I highlight multuiple entities in the floorplanner
Is it possible to highlight several separate entities in the floorplanner, preferably giving each entity a different colour? Currently Im just using the project navigator -> rightclick -> locate...
View ArticleCamera Capture fail de2_70 with TRDB-D5M
Hi, i'm playing with DE2-70 with TRDB-D5M connected. I started from DE2_70_CAMERA project, which was included in bundle. After i get over to download .elf to board and other issue - it finally worked....
View Articleuse of function lpm
Hi to everybody, i write a small machine state to implement the and product separately.. i use std_logic_vector signal, so in the first state i sum the result of the product state.. but i never use lpm...
View ArticleBitstream (.SOF) details
Hi, I would like to know if there are any sheets on Configuration/Bitstream Details for Altera FPGA, explaining the operation codes in the bitstream header, and the general bitstream layout. thanks,
View ArticleLooking VHDL example to do a Component QSYS auto #port
Hi, I am looking for a simple example to make a component QSYS with a configurable port number such as "Merlin Fanout" in VDHL with its TCL. This will help me a lot to learn. Can someone help me. Thank...
View ArticleMax V 5M160ZE64C5 does not contain GND pins
Max V 5M160ZE64C5 does not contain GND pins in orcad symbol olb, nor in quartus pin planner. we (at my work ) discussed this problem and came to result that this is a new quantum CPLD which doesnt...
View ArticleProblem with Qsys when creating PIO
I am beginning to create a hardware with Qsys. The system that I want to create has 4 ports: clk(input), reset(input), a1(input), a2(output). I added a nios processor, a on-chip memory, a jtag uart, a...
View Articletry to find bitstream size and area estimates in Quartus stratix V
Hi 1. Is there a way to find bitstream size of a specific mapping in Quartus? By using .sof file? But it seems to be for total board. Is there a way to find numbers for active/utilized part of a...
View ArticleArria II GX devkit - CFI Flash - probe failed on uCLinux
I've been trying to use the CFI Flash on the "Arria II FPGA Development kit, 6G edition" but I just can't get it to work. The flash is a Numonyx 512P30 (P/N PC28F512P30EF). The error I get during...
View ArticleDe2-sd card
Hi everybody! I have to read files from a SD card using a DE2, can anyone help? Any kind of help...
View ArticleHave to support ancient product with EPM7032 CPLD USB Blaster problems
First time post - please excuse me if this isn't in the correct forum. My company has one board with a discontinued EPM7032 CPLD. We're presently gearing up to do one more "retirement" build of this...
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