I have previously only been working with Xilinx FPGAs, so I need some help to flash to Altera MAX-V which for me seems to be a bit different from the Xilinx flash procedure. The goal is to flash the MAX-V CPLD using JTAG interface.
So far I have created and synthesized the design and assigned pins using the Pin Planner application. I have not assigned any JTAG pins manually in the Pin Planner, but I assume pins 14-17 are already assigned for TMS, TDI, TCK, and TDO respectively as default. I wonder if I need to use some kind of IP core in order to use the JTAG interface to flash?
So far I have created and synthesized the design and assigned pins using the Pin Planner application. I have not assigned any JTAG pins manually in the Pin Planner, but I assume pins 14-17 are already assigned for TMS, TDI, TCK, and TDO respectively as default. I wonder if I need to use some kind of IP core in order to use the JTAG interface to flash?