Generate programmable file for MAX-V CPLD using Quartus Prime Lite
Hi, I have created the hardware design and would now like to generate a programmable file that will be flashed to my MAX-V CPLD. However, just compiling the design in Quartus does not seem to generate...
View Articlecompiler can't fit design despite 1st stage compile reporting low utilization
I'm attempting to compile a kernel for an Arria 10 device. The 1st stage compile completes and reports the following utilization: ALUTS: 31% FFs: 33% RAM: 44% DSP: 10% Despite the design easily fitting...
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DE2-115 control panel issue
I'm a beginner and just started with de2-115 board, i'm not able to connect with the control panel. the following errors show up everytime. I've tried most thing written on other forums. I'm running...
View ArticleNeed advice for my project
HI, I'm trying to run secure hash algorithms on DE2-115. For now i'm not using Nios-II, I want to give inputs through keyboard and display the hash values on a screen, preferably through VGA. I'm just...
View ArticleEP4SGX230HF35C2 pinout
Hi all, I have been trying to do the pin assignment for EP4SGX230 Altera terasic DE4 according to: ftp://ftp.altera.com/up/pub/Intel_Ma...ser_Manual.pdf This user manual is based on EP4SGX530 which...
View ArticleMax10 vs Socs: Differences in Nios II Processors of the two systems.
Hi I have some general questions regarding to differences between Max10 and Socs (e.g. Cyclon V). As far as I understand, Max10 does not have an integrated MCU while Cyclon does have one. However one...
View ArticlePLL Simulation not working fine
Hello, I am using Quartus Prime 17.0 version. In that when I am using PLL IP for clock generation, then during simulation I am not getting continuous clock at the output rather getting continous clock...
View ArticleError (10481): VHDL Use Clause error at firTree32tap.vhd(118): design library...
Hi every one i m using quartus 11.0 sp1 on the ubuntu and got the following error in my code can any body help me how to remove this error.thanks in advance error Error (10481): VHDL Use Clause error...
View ArticleUnrecognizable characters received via NIOS II UART
Hi all, I am configuring my DE0-Nano SOC kit for NIOS based UART communication (RS232). Everything is done as per the available literature. Connections are also done as: GPIO[1] as Rx connected to Tx...
View ArticleMeeting timing requirements with async signal.
Hey everyone. I've been studying computer architecture for some time, but I'm still new to circuit design and VHDL, so this might be obvious, but I still need help. I'm developing a MIPS style...
View ArticleWhat is VHDL equivalent for Verilog $readmemb to initilze RAM/ROM?
The $readmemb() is mentioned in "Recommended Coding Styles" page 12-26. It seems that this can be used in simulation AND synthesis. If one unfortunately uses VHDL rather than Verilog, than how does one...
View ArticleOpenCL_Library : Exemple 1 :Segmentation fault (core dumped)
Hi, I'm trying to excute the example OpenCL Library (Exemple 1) (Link Below). I generated my excutable file for My FPGA Arria 10. Then I get this message when I execute : Segmentation fault (core...
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Quartus 13 jpg image export not working correctly ?
When I click on export from the file menu to export a JPEG image, it seems to totally miss off the top half of the image and I cannot figure out why.. It looks like the image size is correct, but the...
View ArticleQuartus 17 full CPU usage ?
Just installed the latest version 17, I it is maxing out one of my CPU cores 100% ? Version 13 did not do this so I don't know why version 17 is maxing core out :-\
View ArticleProblem with reboot of DE2i-150 Development kit
Hello, I have worked with DE2i-150 Development Kit for 2 weeks. Now, I'm writing simple Kernel driver for Intel Antom Processor to Read/Write GPIO from FPGA. When I develop driver, I'm having some...
View Articlepartitioning __constant cache into parallel local memory banks
Is there a way to partition __constant cache into parallel memory banks? The following code snippet should give some idea of what I'm trying to do. Instead of explicitly moving the message data into...
View ArticleProgram the Altera MAX-V CPLD using JTAG
I have previously only been working with Xilinx FPGAs, so I need some help to flash to Altera MAX-V which for me seems to be a bit different from the Xilinx flash procedure. The goal is to flash the...
View ArticleCyclone IV FPGA communicate with CPU by pcie
hello guys, I use the cpu communicate with fpga by pcie and the cpu is the RP and FPGA is the EP.In RP i can read the EP vender ID , device ID , BAR mask and allocate pcie address for EP.but when i...
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How to infer BRAM fan-out
I am doing an OpenCL project of vector multiplication of VecA (m * 1) and VecB (1 * n) which produces a matrix MatC (m * n). I want to use a fan-out design which can support a 2-D processing engine...
View ArticleInstantiate a Custom Register Map interworking with HPS and PCie Avalon MM
Hi to all, I've a bunch of registers managed with our internal bus protocol, so we should insert a Avalon MM bridge to translate our protocol .(It is a propietary bus protocol used by our company in...
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