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Unconstrained Path in PFL IP core
Hallo I am making a PFL IP core for a MAX V device. and i wrote a SDC file based on the application note 478,the PFL IP core user guide. which is available on the following link. I used table 7 from...
View ArticleArria 10 PCIe Gen 3 timing violations in Quartus 17.0.2
I got timing violations in Arria 10 PCIe Gen 3 design after upgrading to Quartus 17.0.2. The same design compiles without timing violations in Quartus 16. Code: Path #1: Setup slack is -4.551...
View ArticleNIOS II/f altera_avalon_i2c, possible BUG in HAL
Hi, I need a I2C master for my NIOS II/f. I thought using the I2C master which is shipped by Altera in Quartus Prime 17.0 should serve my needs. However I'm a bit worried about the software quality of...
View ArticleQuartus accepts `endif within quoted String "`endif // foo" as endif ?
I am using Quartus Prime Lite 17.0.0 and it accepts the following file: Code: module ParserErrorV01( input wire D0, output wire LED1 ) ; Â reg [10*8:1] s ; Â assign LED1=D0 ; Â Â `ifdef POSEDGE Â s =...
View ArticleI can not able to configure fpga to quartus
Dear All, I am sasi, Trying to program the fpga , But I can not able to do it.I configer the jtag usb blaster ii, they are perfectly fine , the only problem is I can not see any hardware configuration...
View ArticleRTL Simulation
Hello, I have been using ModelSim-Altera for my RLT simulations of my FPGA designs. I usually go to Tools->Run Simulation Tool->RTL Simulation and then ModelSim launches, compiles my project, run...
View ArticleBLVDS termination for MAX 10
I am using a MAX 10 to drive another chip using LVDS. I am using the true LVDS driver. I would like tobe able to Tri-State the LVDS driver when the power to the chip that I am driving is not enabled....
View ArticleQuartus crash
Why am I having this problem, anyone have idea pls? Quote: Problem Details Error: Internal Error: Sub-system: FSAC, File: /quartus/fitter/fsac/fsac_ram_packing_estimator.cpp, Line: 130...
View ArticleDoing a "diff" on two seperate .qpf files
A couple of us students in class generated a design in Qsys that includes a NIOS II and several other modules that are irrelevant in mentioning here. We also wrote a c application in eclipse and...
View ArticleVIP SCALER II output data all zero
When I run the SCALER II with no control port, I use the bicubic way. And I have no .mif file The control packet can output correctly, but the video packet output is all zero. The valid, ready, sop and...
View ArticleSPI ram and Nios on FPGA MAX10
Hi all, Is it possible connect a SPI ram (single or quad) to the NiosII in Qsys and allocate/use (from C code in Eclipse) my data in this ram? Thanks in advance. Perryiavo
View Article#pragma ivdep not allowing for parallel stores to local memory
Hello, I am having difficulty in parallelizing local memory store operations and would appreciate help. The load from local memory appears to be parallelized however in the report.html's System Viewer...
View ArticleAvalon Memory Mapped pipelined slave writes
I have been creating Avalon Memory Mapped master and slave interfaces for my custom components in my system. I have read through the Avalon specification multiple times, but I find one aspect of it...
View ArticleterasIC DE10-Nano Windows DS-5 Example
I am trying to cross compile a simple C++ "Hello World" program from Windows using Eclipse for DS-5 to the terasIC DE10-Nano running Angstrom Linux. However, when trying to run it I get a segmentation...
View ArticleAvalon Memory Mapped pipelined slave writes
I have been creating Avalon Memory Mapped master and slave interfaces for my custom components in my system. I have read through the Avalon specification multiple times, but I find one aspect of it...
View ArticleObtain a pof from MAX 10 internal flash?
Hi there, I had a .pof file that I programmed onto the MAX 10 awhile ago but I seem to have lost that file and my project. Is there a way to obtain that pof from the internal flash of Max 10 so I can...
View ArticleQuartus flow hangs after completion.
Quartus run's to completion, but at the end of the run the GUI freezes up and has to be killed. I have a design that contains several NIOS cores and DDR4 controllers. Until recently I there was only a...
View ArticleUSB Blaster for DE1 board
Hi, I am new to Altera DE1 board. When I connected DE1 board, "found new hardware" window is not popping up in windows 8.1 computer. What should I do to install USB blaster...???? TIA.
View ArticleVHDL Error. Type of identifier does not agree with it's usage
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std; entity multi_main_file is port( Clock,reset: in std_logic ); end...
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