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NIOS II/f altera_avalon_i2c, possible BUG in HAL

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Hi,

I need a I2C master for my NIOS II/f. I thought using the I2C master which is shipped by Altera in Quartus Prime 17.0 should serve my needs.
However I'm a bit worried about the software quality of the HAL and drivers.

While testing I recognized that switching speed of the bus is not possible. The clock setting is fixed for 100kHz, setting other values results in wrong behaviour.

altera_avalon_i2c.c:302
Code:

ALT_AVALON_I2C_STATUS_CODE alt_avalon_i2c_master_config_speed_set(
  ...
  /* adjust h/l by predetermined amount */
  scl_hcnt = scl_lcnt + ALT_AVALON_I2C_DIFF_LCNT_HCNT;  // scl_lcnt+60, should be scl_lcnt+15 for 400kHz
  scl_lcnt = scl_lcnt - ALT_AVALON_I2C_DIFF_LCNT_HCNT;
  ...

Therefore ALT_AVALON_I2C_DIFF_LCNT_HCNT should be adapted to the speed setting.

Did I miss something? What is your experience with the NIOS II software drivers?

In addition, I could not find any proper documentation with examples. Do I really have to browse the header files to get infos about the API?

Cheers, Marc

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