I got timing violations in Arria 10 PCIe Gen 3 design after upgrading to Quartus 17.0.2. The same design compiles without timing violations in Quartus 16.
The problem is that this path is completely inside encrypted part of PCIe IP.
Is there a workaround? Quartus bug fix?
Code:
Path #1: Setup slack is -4.551 (VIOLATED)
; From Node ; top:top|top_altera_pcie_a10_hip_170_ueiagsq:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|wys~ch3_pcs_chnl_hip_clk_out[0].reg
; To Node ; top:top|top_altera_pcie_a10_hip_170_ueiagsq:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3
x8|top_altera_xcvr_native_a10_170_ylcxrpq:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm2:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm2:inst_twentynm_pcs
|gen_twentynm_hssi_common_pld_pcs_interface.inst_twentynm_hssi_common_pld_pcs_interface~pld_rate_reg.reg ;
; Launch Clock ; top|pcie_a10_hip_0|tx_serial_clk
; Latch Clock ; top|pcie_a10_hip_0|pll_serial_clk_8g
; Data Arrival Time ; 7.020
; Data Required Time ; 2.469
; Slack ; -4.551 (VIOLATED)
+---------------------------------------------------------------------------------------+
; Statistics ;
+---------------------------+--------+-------+-------------+------------+-------+-------+
; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ;
+---------------------------+--------+-------+-------------+------------+-------+-------+
; Setup Relationship ; 0.050 ; ; ; ; ; ;
; Clock Skew ; -1.856 ; ; ; ; ; ;
; Data Delay ; 2.221 ; ; ; ; ; ;
; Number of Logic Levels ; ; 0 ; ; ; ; ;
; Physical Delays ; ; ; ; ; ; ;
; Arrival Path ; ; ; ; ; ; ;
; Clock ; ; ; ; ; ; ;
; Clock Network (Lumped) ; ; 1 ; 3.599 ; 100 ; 3.599 ; 3.599 ;
; Data ; ; ; ; ; ; ;
; IC ; ; 1 ; 0.001 ; 0 ; 0.001 ; 0.001 ;
; Cell ; ; 1 ; 0.000 ; 0 ; 0.000 ; 0.000 ;
; uTco ; ; 1 ; 2.220 ; 100 ; 2.220 ; 2.220 ;
; Required Path ; ; ; ; ; ; ;
; Clock ; ; ; ; ; ; ;
; Clock Network (Lumped) ; ; 1 ; 1.743 ; 100 ; 1.743 ; 1.743 ;
+---------------------------+--------+-------+-------------+------------+-------+-------+Is there a workaround? Quartus bug fix?