sending 64 bit from fpga to hs to terminal in pc @10k
hi, i had a terasic sockit (which had a cyclone 5 soc). i already implemented sending 64 bit data from fpga to pc by using nios2 processor ( nios2+jtag uart_onchipram). but its speeed is very...
View ArticleCan't find spi/i2c HAL's API in handbook
Hello, I am new with NIOS II. For now, I first try to verify that we have the required APIs. But searching for spi/i2c APIs in hal reference in "NIOS II Software development handbook", I did not find...
View ArticleMax10 on-chip-flash (UFM) resource utlisation
I have instantiated the 'Altera On-Chip Flash' megafunction to access the UFM on a 10M04DCF256 device. 1) There seems to be a discrepancy between the documentation and the tools in Quartus Prime...
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Error (169175): Pin # with LVDS I/O standard needs a differential output?
Hi, I'm using a Terasic DE10-lite board with a 10M50DAF484C7G MAX 10. I'm trying to use some LVDS differential outputs but I get this error: Code: Error (169175): Pin "GPIO[14]" with LVDS I/O standard...
View ArticleCreating my own interface standard
Hi, I want to do an FPGA project, and for this "rather than using USB" id like to see if I can do a custom serial interface standard. The main reason being, I dont want to deal with handshakes and pull...
View ArticleUSB blaster recognized by one Quartus version but not others
I have Quartus II 8.0, 9.0 and 12.0 Web Editions installed on my Windows 7 computer. Only version 8.0 recognizes the USB blaster cable. But I need version 12 now. I tried to uninstall/install and...
View ArticleDoes the compiler add or omitted unused gates ?
For example, if I had a 74244 buffer, and only used 4 buffers, and I do not connected the other 4 buffers to anything, would the compiler still add those unused gates into the PLD logic blocks ? Or...
View ArticleBoot C5 HPS from SD card
I try to boot C5 HPS from a SD card. I get the following information from UART0 ----------------------------------------------------------------------- U-Boot SPL 2013.01.01 (Oct 23 2017 - 14:37:32)...
View ArticleA new device driver always requires HAL ?
Hello, I am new with NIOS II. I would like to ask a general question, does it require to use HAL with each new device ? Regards, Ran
View ArticleCyclone V SoC: Baremetal debugging
Hello, I am trying to debug the Cyclone V SoC using a bare metal debugging. But, it shows me an error while I starts debugging. "Unable to connect to TCP:local host" So, what should be the reason...
View ArticleDoes .sof is used with qspi ?
Hello shaiko, According to section 1.7.2 in this document https://www.altera.com/content/dam/a...e/an/an741.pdf the .sof file is used to program qspi. But I thought that sof is used only for volatile...
View ArticleI want to know which type of fpga I am using(ex: GT,Extended features or Base..)
My Board is DE1 fpga : 5csema5f31c6nf please help me to configure my board thanks
View ArticleCan't load .jic file to EPCQ device.
Hello, I am trying to load the .jic file to EPCQ 128 (Part no.:- S25FL128SAGMFBG00) but it shows me an error. Error message: Error (209025): Can't recognize silicon ID for device 1. A device's silicon...
View ArticleAltfp_sincos
I am intending to use the ALTFP_SINCOS core in my design. I am just wondering why there is not the possibility to choose the NaN status port in the megawizard? Any clues on that? Jusuf
View ArticleUSB Blaster shows up in device manager under Ports (COM & LPT) as a USB...
Hi all! I have a Dell Inspiron laptop running Windows 10, and I have a DE2-70 kit. When I plug in the USB blaster, nothing happens, and I go to the device manager, and it shows up in device manager...
View ArticleCyclone II Obsolete part replacement
Is there a pin compatible part replacement for Cyclone II EP2C20F256C6 part?
View ArticleChannel non-blocking write semantics.
Hi. I noticed that - in emulation - a non-blocking write may also send data to a channel when it reports a failure. There is one blocking read on the other side that receives more than it should. Is...
View ArticleAvalon Memory-Mapped Master Templates with Quatus 14.1
Hi all, Can you send for me Avalon Memory-Mapped Master Templates IP for quartus 14.1. I want read data RAM onchip from qsys by verilog core. Thanks.
View ArticlePosters "On Behalf of Intel"
I See a few posters now with the signature "(This message was posted on behalf of Intel Corporation)". They seem to be digging up old posts to reply with very short answers. Given all of these posters...
View ArticleConstraint Qsys IP Addressable Memory Range
Hi everyone, A few weeks ago I migrated from Xilinx to Altera/Intel ecosystem and I am facing some problems that I don't know how to fix because of the lack of experience with Quartus tool. I am...
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