Hi everyone,
A few weeks ago I migrated from Xilinx to Altera/Intel ecosystem and I am facing some problems that I don't know how to fix because of the lack of experience with Quartus tool.
I am designing a Qsys system with a Nios II processor, some peripherals (I2C, SPI, etc...), and a DDR interface. The design is really simple, I can test each interface separately and they work properly, but I am struggling with the Address Map of the system as soon as I connect everything together.
The DDR interface a 4GB SODIMM DDR4 module, and as soon as I instantiate the IP in the system it takes the whole addressable space of the Nios II processor (32bits), leaving the other peripherals unreachable. My Idea was to restrict the Nios access to the DDR to only 2GB, so I will be able to access all the devices of my system to achieve more complex test of the application software. My question is:
I tried under the Address Map tab in Qsys, but I can only change the base address of the peripheral and not the addressable range/high address. I assume should be a way to configure the Avalon-MM interconnects and restrict the addressable range, but I found nothing.
Surely it is really easy, but I can not find that option. Any ideas?
Thanks for your time!
A few weeks ago I migrated from Xilinx to Altera/Intel ecosystem and I am facing some problems that I don't know how to fix because of the lack of experience with Quartus tool.
I am designing a Qsys system with a Nios II processor, some peripherals (I2C, SPI, etc...), and a DDR interface. The design is really simple, I can test each interface separately and they work properly, but I am struggling with the Address Map of the system as soon as I connect everything together.
The DDR interface a 4GB SODIMM DDR4 module, and as soon as I instantiate the IP in the system it takes the whole addressable space of the Nios II processor (32bits), leaving the other peripherals unreachable. My Idea was to restrict the Nios access to the DDR to only 2GB, so I will be able to access all the devices of my system to achieve more complex test of the application software. My question is:
- Is it possible to restrict the addressable memory of a peripheral in Qsys?
I tried under the Address Map tab in Qsys, but I can only change the base address of the peripheral and not the addressable range/high address. I assume should be a way to configure the Avalon-MM interconnects and restrict the addressable range, but I found nothing.
Surely it is really easy, but I can not find that option. Any ideas?
Thanks for your time!