Enable DEV_CLRn in MAX-V
Hi, I would like to enable DEV_CLRn on pin 29 in order to do a device clear. However, it seems to be set to user I/O whenever I enable the pin in Quartus. How can I set the pin to be DEV_CLRn? Thanks.
View ArticleCyclone V clock pin driver output impedance
Dear all, I am using a Cyclone V 5CSXFC6D6F31C6N on a TerasIC SocKit developer board to produce two coherent clock signals via the PLLs of the FPGA. To get those clock signals of-chip, the TerasIC...
View ArticleError while running in quartus
Dear all, Due to this line in my project I got errors LEDR <= std_logic_vector(to_unsigned(result,10) ); this is my error in my project Error (10029): Constant driver at lb.vhd(65) Error (10028):...
View ArticleState machine counter problems
I do not understand why my state machine does absolutely nothing. Can anyone identify why? It seems simple enough to me, 4 states that have three possibilities based on two inputs (2 state changes and...
View ArticleAltera "My Support" is down..
Has anyone also noticed this? For the past few days, I have been unable to create a Service Request with Altera.. Pl refer to my following forum...
View ArticleHow do I convert verilog file to board symbol file using quartus?
Hi, To convert the *.v file to *.bsf, I tried to go to File -> Create/Update -> Create Symbol Files for Current File. But this option is greyed out. I'm using Quartus version 16. I remember this...
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Block Diagram Display Issue
Hi, I am an engineering student running the Quartus Prime Lite edition for work in my digital logic design class. I'm enjoying the program on my desktop but I'm having some display issues on my laptop...
View ArticleError generating simulation files for Qsys system
I have a design using Cyclone IV, Quartus 17.0 I have a Qsys system that includes a NIOS, DRAM controller, several standard peripherals, and then several IP blocks of my own design. I can generate the...
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DE10-Lite accelerometer with NIOS using University Program IP
I have a number of students who would like to use the DE10-lite accelerometer for their class projects. We cannot seem to get this working within the NIOS system using the University Program...
View ArticleMAX V add pull up resistor for input
Hi Guys, I'm not sure how to add a pull up resistor for an input pin using Quartus Prime? I try to find it in Pin planner and assignment, but there is nothing shows to add a pull up resistor. Thanks!
View ArticleCan HPS verify FPGA configuration?
I have a Terasic DE-10 kit, and some of the sample programs require me to program the FPGA externally through JTAG and then run a program on the HPS which utilizes this configuration. Is there any way...
View ArticleDoes Max10 SCE have no ability to "Select Internal Configuration mode with...
Hello, I have a question. I am using a 10M50SCE144C8G chip. (i.e. MAX 10 SCE chip) and Quartus Prime Version 17.0.0 Build 595 (04/25/2017) SJ Lite Edition. I have my VHDL code loaded into CFM0 and that...
View ArticleGeneral question about EEPROM
Hi I recently had a problem with my dev kit- when I plugged it in to my computer, it showed up as a USB serial device as opposed to a USB blaster. The extremely helpful forummers here informed me that...
View ArticleI cant find any mistake but my compiler says its a mistake
Dear all, Please help me out her. counter <= counter + '1'; this is my instruction this is my error. So what is the mistake in it? Error (10327): VHDL error at led_blink.vhd(24): can't determine...
View ArticleMAX10 UFM writing takes much longer than expected
Hi Folks, in my design on a MAX10 10m08sau169 I am using the internal user flash UFM to store some data. I am NOT using a NIOS to do the writing through the avalon interface. Instead of this I have...
View ArticleForcing loop iterations to execute sequentially
Hi all, I have some code that has a nested for loop in a single work item kernel like so: __local lmem[M][2]; // ping pong buffer for (uint outer = 0; outer < N; ++outer) {__private wr_bank_sel =...
View Articlequestions about buffer size and parameter size.
I am implementing sparse matrix multiply on Nalla 510t, and have some problem transfer my matrix. The problem has I stripped the matrix into 512 pieces for parallel computation. First I tried to create...
View Article"For... Loop" simulates differently then discrete assignments?
Can someone help me understand why the first code snippet works as I would expect it, but the second snippet simulation holds all values at 'U'? Note: WRITE_ENABLE_FIBRE_REG(0) is assigned in a...
View ArticleNios II: Is there a way to control mapping of low-level resources to MLABs?
Hi Fellow Forumers, I'm up against the limit of available M20K RAM blocks in a design and desperately fighting to regain blocks wherever I can. In the .fit report, I note that my Nios designs (I have...
View ArticleCould not handle interrupt on E0-Nano-SoC Altera 5CSEMA4U23
We have built linux kernel from https://github.com/altera-opensource...ee/socfpga-4.6 and set it on DE0-Nano-SoC Altera 5CSEMA4U23. Now we are trying to throw interrupt 77 from FPGA and handle it in...
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