Dear all,
I am using a Cyclone V 5CSXFC6D6F31C6N on a TerasIC SocKit developer board to produce two coherent clock signals via the PLLs of the FPGA. To get those clock signals of-chip, the TerasIC XTS-HSMC break-out board is used. Looking at the resulting signals via an scope (KeySight DSO3054T) using a high input impedance, they look quite messy. Typically, these kind of signals are 50 Ohm terminated. So it could be that the messyness of the signals is a result of reflections due to poor termination. However I am not sure if the FPGA can drive a 50 Ohm load. Most pins could only proivde something like 8 to 12 mA. Using the 2.5 Vpp output swing to drive a 50 Ohm load is than asking for problems.
Due to board limitations, the output of the PLLs is routed via PINs A10 and A11. According to quartus and the pin information of altera these pins have the special function of FPLL_TL_CLKOUTn (A10) and FPLL_TL_CLKOUTp (A11). I think (according to the Technology Map Viewer of Quartus) that the pins are driven bij a buffer called "IO_OBUF", although I could not find any additional infromation about this buffer on the internet.
Based on the special function I think pins A10 and A11 could drive a 50 ohm termination impedance, because it is quite standard to use a 50 ohm transmission line and 50 Ohm termination impedance. However I have been googling, reading, and searching the web for over a day and have not yet found any information which confirms or rejects this assumption. Does anyone here knows if I could safely terminate pins A10 and A11 with a 50 Ohm impedance?
Thanks in advance :)
With kind regards,
Wobbert
I am using a Cyclone V 5CSXFC6D6F31C6N on a TerasIC SocKit developer board to produce two coherent clock signals via the PLLs of the FPGA. To get those clock signals of-chip, the TerasIC XTS-HSMC break-out board is used. Looking at the resulting signals via an scope (KeySight DSO3054T) using a high input impedance, they look quite messy. Typically, these kind of signals are 50 Ohm terminated. So it could be that the messyness of the signals is a result of reflections due to poor termination. However I am not sure if the FPGA can drive a 50 Ohm load. Most pins could only proivde something like 8 to 12 mA. Using the 2.5 Vpp output swing to drive a 50 Ohm load is than asking for problems.
Due to board limitations, the output of the PLLs is routed via PINs A10 and A11. According to quartus and the pin information of altera these pins have the special function of FPLL_TL_CLKOUTn (A10) and FPLL_TL_CLKOUTp (A11). I think (according to the Technology Map Viewer of Quartus) that the pins are driven bij a buffer called "IO_OBUF", although I could not find any additional infromation about this buffer on the internet.
Based on the special function I think pins A10 and A11 could drive a 50 ohm termination impedance, because it is quite standard to use a 50 ohm transmission line and 50 Ohm termination impedance. However I have been googling, reading, and searching the web for over a day and have not yet found any information which confirms or rejects this assumption. Does anyone here knows if I could safely terminate pins A10 and A11 with a 50 Ohm impedance?
Thanks in advance :)
With kind regards,
Wobbert