Hi all.
I currently develop a board with a Cyclone III (EP3C25) device. I want to have opinions on my configuration / reset circuit diagram (see attached file).
The choices that i have made are :
- use of active serial configuration scheme with EPCS16 device
- use of JTAG for debug (SOF) and programming (JIC via SFL) as i have not enougth space on board to place the two connectors
- use of MAX823 supervisor to :
. restart configuration on power-up or when power fails or if watchdog occurs (ie if the blinking led is halted)
. create additonnal 140ms reset time after end of configuration to reset the internal FPGA logic previously configured
- creates "basic" VCCA with serie's diode and 10µF decoupling capacitors
- takes attention on active serial and JTAG ports to avoid dangerous overshoots :
. 47u serie's resistance on DATA0 of EPCS device (value to be confirmed)
. 47u / 100pF line adaptation to avoid EPCS DCLK transmission line reflexion (seen only on that signal on real board with equal lenth epcs non adapted lines)
. JTAG io level powered by VCCA (2.5V) to reduce JTAG levels produce by usb blaster (ie limit overshoot risks)
. MSEL pin configuration directly to gnd or vcca
. serie's resistance on TDO signal and additionnal pull-up as seen on some evaluation board schematics
. line adaptation on 4 JTAG signals as connected to non adapted usb blaster cable (as additionnal precaution to 2.5v powered jtag)
My interrogations are :
- first are my precautions sufficient to prevent FPGA damages ? (these FPGA seems to be quite "sensible")
- as i have never use SFL, is it a signicative time performance degradation when flashing epcs via JTAG ?
- i plan to populate my 470pF capacitor between the max823 supervisor and nConfig pin only when i have finish to debug as i think have a risk that my watchdog restart the configuration when i use JTAG loader : in others words what is the priority between SFL and EPCS config circuitry ?
- has anyone notes line reflexions on DCLK line ONLY (ie not on nCS and ASDI epcs lines ???)
Thanks.
Best Regards.
I currently develop a board with a Cyclone III (EP3C25) device. I want to have opinions on my configuration / reset circuit diagram (see attached file).
The choices that i have made are :
- use of active serial configuration scheme with EPCS16 device
- use of JTAG for debug (SOF) and programming (JIC via SFL) as i have not enougth space on board to place the two connectors
- use of MAX823 supervisor to :
. restart configuration on power-up or when power fails or if watchdog occurs (ie if the blinking led is halted)
. create additonnal 140ms reset time after end of configuration to reset the internal FPGA logic previously configured
- creates "basic" VCCA with serie's diode and 10µF decoupling capacitors
- takes attention on active serial and JTAG ports to avoid dangerous overshoots :
. 47u serie's resistance on DATA0 of EPCS device (value to be confirmed)
. 47u / 100pF line adaptation to avoid EPCS DCLK transmission line reflexion (seen only on that signal on real board with equal lenth epcs non adapted lines)
. JTAG io level powered by VCCA (2.5V) to reduce JTAG levels produce by usb blaster (ie limit overshoot risks)
. MSEL pin configuration directly to gnd or vcca
. serie's resistance on TDO signal and additionnal pull-up as seen on some evaluation board schematics
. line adaptation on 4 JTAG signals as connected to non adapted usb blaster cable (as additionnal precaution to 2.5v powered jtag)
My interrogations are :
- first are my precautions sufficient to prevent FPGA damages ? (these FPGA seems to be quite "sensible")
- as i have never use SFL, is it a signicative time performance degradation when flashing epcs via JTAG ?
- i plan to populate my 470pF capacitor between the max823 supervisor and nConfig pin only when i have finish to debug as i think have a risk that my watchdog restart the configuration when i use JTAG loader : in others words what is the priority between SFL and EPCS config circuitry ?
- has anyone notes line reflexions on DCLK line ONLY (ie not on nCS and ASDI epcs lines ???)
Thanks.
Best Regards.