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Pin assignment for Flash and SDRAM of DE2-70
Dear my friends I wanna make pin assignments for flash and Sdram of DE2-70 altera kit but I don't know which one is correct. Could you check it for me (I've attached it in this message)? what is the...
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Need help ASAP! 16-bit single cycle processor
I am supposed to program a 16-bit single cycle (also multi-cycle, but we'll stick with the single cycle for now) processor. All requirements are below. I have a simple data path, but honestly, I wasn't...
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Astronomer requesting Developemnt Feedback/Guidance (CycIII, Verilog)
Hi All, First off: I'm an astronomer way out of my comfort zone! Second: I'm essentially asking for people to look at what I'm working on, talk about it with me, point out how I've screwed it up, and...
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NIOS 2 alt_up_charactor_lcd to display variables C program
hey guys i need help with this i know how write to the LCD display, i just don know how to get my variables to display if you check my code you will see what i mean. Code: #include...
View Articlehow to do a further development on uclinux
Hello, I am a beginner, I have been on the development board to build a basic uclinux operating system, but I do not know what to do next, how to do a further development, such as add my own codes or...
View ArticleDDR2 interface pin planning issue
Hello, I'm working on a design that is going to use a Cyclone IV FPGA (EPCE75) including migration support for the EPCE30 and EPCE40 devices (F780 package). A lot of IO's will have to operate at 3.3V...
View ArticleModelSim + for loop generation + nonresolved signal has multiple sources error
Hello All, I am trying to compile the following code in modelsim and getting "nonresolved signal RX_CH_A has multiple sources. Code: -- In process 1 Â Â Â Â Â Â for i in 0 to 5 loop...
View Articlequartus II licence
hi all.. i downloaded and install quartus II v7.0 . its 30 day trial version . how to get its free licence key or activation key . it just compile but dont creat programming file .. plz help me ...
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Cyclone III reset and configuration
Hi all. I currently develop a board with a Cyclone III (EP3C25) device. I want to have opinions on my configuration / reset circuit diagram (see attached file). The choices that i have made are : - use...
View ArticleBidirectional pins in schematic entry
I am attempting to connect to a nand flash device with shared input/output data and command pins. I am using schematic entry for my Quartus top level design and I have added bidirectional pins that...
View ArticleNeed help with VHDL-project
Hi I'm working on a vending machine project. The VHDL code for the entity is in this pastie: (pastie.org/5475527) I need some help with getting the system to do what I want. As it is now, when one of...
View ArticleEpcs16 configuration
Can i configure the serial configuration device (epcs16) without having the fpga in the circuit? If so how? I couldn't find any documentation on it
View ArticleGeneric component inside generic component
Hello.I am designing a vhdl code that has a generic size setting a bunch of operations.I cannot synthetize it with quartus (Error (10346): VHDL error at mac.vhd(7): formal port or parameter "width"...
View ArticleWhat are Simulink toolboxes needed to run Cholesky Solver w/ Altera Advanced DSP
When I compiled an example of Altera Adv DSP builder: Cholesky solver, there are several fixed point license errors. After ran Simulink Model Advisor, there are the following errors Check for...
View ArticleDM9000a slow receive packet!
Hello everyone, I have a board DE2 (EP2C35 with DM9000a module). I'm using driver include with CD, I send UDP packet (1440 byte) from the PC to FPGA via DM9000a but the receive packet is too slow about...
View ArticleImplementing firmware version
I am trying to make a code that can store firmware versions from a .txt file, I tried doing it with a ROM initialized with a .mif file, but it's not working. I have a Cyclone III that sends that info...
View Articlechange link address
Bonjour I have a nioII/e in a cycloneIII+EPCS4 with only internal memory , an uart , a PIO and no debugger . It is run and I can dialog with the Uart , all is OK. But I must to compile with Quartus and...
View ArticleNIOS II SOC Simulation with altera_avalon_mm_master_bfm
I have designed an SOC with NIOS II using QSYS. The design works in HW with SW running. Now, I want to simulate the SOC using the altera_avalon_mm_master_bfm. What I am not clear about is, do I simply...
View ArticleMulti source?
Hello. I am trying to make a mac component. Everything is fine, until I put acc (my accumulator) receiving the output value. The strange thing is that Quartus sythetize it, but Modelsim acuse a...
View ArticleChanging the clock rate on the Audio SRC
Hi, My company has the Altera Audio SRC IP running on a Cyclone III, and we're thinking of changing the clock rate from the 98.304MHz clock to a 150MHz clock. Can this be easily done? After looking at...
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