Hi,
Having problems generating a simple mixed dual port RAM using M10 block memory. Using Quartus 16.1.0 Build 196, for CycloneV SX (5CSXFC6D6F31C6) FPGA. Trying to generate an Oncip RAM with the parameters shown on the image.![]()
Compiling the generated files produces the following error:
Error (272006): Cannot use port A width with port B width in altsyncram megafunction
PortA width is 64 bits, PortB width is 256 (i.e. mixed width ratio is 4). According to Embedded Memory User Guide (and the Megawizzard Manager itself) this is a valid combination of mixed-width. To be specific, UG-01068 | 2017.11.06, 3.5 Mixed-width Ratio Configuration: for True Dual Port Memory without Byte enable valid ratios are 1, 2, 4, 8, and 16.
What is wrong?
Having problems generating a simple mixed dual port RAM using M10 block memory. Using Quartus 16.1.0 Build 196, for CycloneV SX (5CSXFC6D6F31C6) FPGA. Trying to generate an Oncip RAM with the parameters shown on the image.
Compiling the generated files produces the following error:
Error (272006): Cannot use port A width with port B width in altsyncram megafunction
PortA width is 64 bits, PortB width is 256 (i.e. mixed width ratio is 4). According to Embedded Memory User Guide (and the Megawizzard Manager itself) this is a valid combination of mixed-width. To be specific, UG-01068 | 2017.11.06, 3.5 Mixed-width Ratio Configuration: for True Dual Port Memory without Byte enable valid ratios are 1, 2, 4, 8, and 16.
What is wrong?