Intel HLS example reports
Hello, I am new to the concept of HLS. I am using Intel HLS and going to start with the examples that come with the installation of Quartus prime edition. Can anyone of you share the successful project...
View ArticlePhysical address of global memory in a device
Hello everyone, I am currently using an OpenCL-enabled Bittware S5-PCIe-HQ board and I plan to create an OpenCL codesign between GPU and this FPGA. My idea is to split kernels between both devices and...
View ArticleCYCLONE III Configuration Device
Will a MT25QL128 work as a configuration device for a CYCLONE III ?
View ArticleStratix 10 MX HBM2
Hello, does anyone know if the HBM2 interface is connected only to the ARM side or the FPGA side? I'm interested in this device because of the 16GB of memory not the embedded ARM cores and have no...
View ArticleThe Jtag pins of the EPM7128s Cpld (MAX7000) can be used as IOs?
Hi, I'm doing a little project with an old Max 7000 EPM7128S Cpld. I'm already using all normal IOs, but I need four more. Seems that the Jtag pins can be used as IOs. Is it true? If so, how the Cpld...
View ArticlePassing parameter/generic to the top level in Quartus/tcl?
I'm trying to pass a git sha1 as a parameter to the top level in Quartus tcl I added a source probe: Code:  gits   u_gits    (.probe (160'habbaface000000000000000000000000acdcbabe)); Which I can...
View ArticlePrinting on B size (11"x17") Paper
I am trying to print in landscape mode on B size paper which is 11" x 17" without any luck. I saw this 'Solution': https://www.altera.com/support/suppo...192012_40.html which is from almost five (5)...
View ArticleCyclone 10LP and Cyclone 10GX - Are they really new?
Dear all, I had planned to use 10LP in my newest designs but after going through some online discussions I saw that 10LP is 60nm nothing but, Cyclone III essentially renamed. Similarly, 10GX is Arria...
View ArticleDesign Template for Arrow Max1000
Hi, Is there any design template available for Arrow Max1000 IoT maker board? Or is there a getting started document? Thanks, Manu
View ArticleGenerate a bianry code from an integer array?
Hello! I am trying to work for first time with integer arrays. I am not so used to work with them, and I am not able to compile my code. At first, I have created a package, for the arrays of integers:...
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Flash Programmer problem
Hello, I´m beginner in Nios II and I´m trying to run project from Altera page as is instructed in Nios II System Architect Design (https://www.altera.co.jp/content/dam..._architect.pdf), Files were...
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Altsyncram mixed port width issue
Hi, Having problems generating a simple mixed dual port RAM using M10 block memory. Using Quartus 16.1.0 Build 196, for CycloneV SX (5CSXFC6D6F31C6) FPGA. Trying to generate an Oncip RAM with the...
View ArticleNo Fmax for memory
I tried to synthesise following code (straight from Altera manual for inferring RAM) to gauge the M20K performance. It compiles fine and I see from the .pin reports that all the inputs/outputs are...
View ArticleQuartus Prime Standard Edition - Evaluation license
Hi, I am new to Altera, and came across Quartus prime tool evaluation feature. And it is mentioned in 'Intel FPGA Software installation and licensing' document that it allows to use the tool for 30...
View ArticleHow to not assign outputs to any pins and avoid being optimized out
Hello, Is it a must to assign outputs of circuit to pins in FPGA? I have a ASIC design of an AES cipher that I want to test on FPGA, but I don't really want to connect the outputs of the circuit to any...
View ArticleHow can I make the Marvell 88E1111 operate in GMII instead of RGMII?
Hi, I've recently gotten the ETHERNET-HSMC Card for use with the Cyclone V GX Starter Kit. Problem: It uses RGMII by default, and I want GMII. The manual just says that this can be changed through the...
View ArticleSignal Tap does not support the OpenCore Plus Hardware Evaluation feature
I am trying to build a simple NIOS system in a MAX10 using Quartus 17.0 and Qsys but I keep getting this set of warnings: Warning (12189): OpenCore Simulation-Only Evaluation feature is turned on for...
View ArticleBlock Design Pin Connection Issues
Hello, I'm having a weird one off problem with Quartus Prime 16.1 on a Windows 10 machine. When adding symbols and pins(inputs, outputs, etc...) the nodes appear to connect but dragging either the pins...
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Single work item Task parallel OpenCL kernel
Hi, Does the following code, invokes the kernel to run like the attached image? or they runs one after another ? Code: clCreateCommandQueue(context, device, NULL, &status); clEnqueueTask(command,...
View ArticleIntel HLS example reports
Hello, I am new to the concept of HLS. I am using Intel HLS and going to start with the examples that come with the installation of Quartus prime edition. Can anyone of you share the successful project...
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