Hello, world!
I am a student working on my thesis. I am in the stage of knowing my tools and Intel HLS compiler is one of them. I know some things about Verilog HDL and some basic use of ModelSim and Quartus.
I have set up a Windows 10 computer to work with. I have installed the required software, Microsoft Visual Studio 2010, ModelSim Intel FPGA Starter Edition 10.5b and Quartus Prime 17.1 Lite Edition.
Following the Intel High Level Synthesis (HLS) Compiler Getting Started Guide, I ran the init_hls.bat in C:\intelFPGA_lite\17.1\hls and set up the environmental variables.
Next I have tried to compile and simulate the counter example.
This also created the test-fpga.prj folder with 4 subfolders: components, quartus, reports, verification
The contents of verification are:
Now I need to simulate the component in ModelSim.
Can someone help me with step-by-step instructions on how to run simulation![]()
I am a student working on my thesis. I am in the stage of knowing my tools and Intel HLS compiler is one of them. I know some things about Verilog HDL and some basic use of ModelSim and Quartus.
I have set up a Windows 10 computer to work with. I have installed the required software, Microsoft Visual Studio 2010, ModelSim Intel FPGA Starter Edition 10.5b and Quartus Prime 17.1 Lite Edition.
Following the Intel High Level Synthesis (HLS) Compiler Getting Started Guide, I ran the init_hls.bat in C:\intelFPGA_lite\17.1\hls and set up the environmental variables.
Next I have tried to compile and simulate the counter example.
Code:
C:\intelFPGA_lite\17.1\hls\examples\counter>build test-fpga
i++ -march=CycloneV counter.cpp -o test-fpga.exe
test-fpga.exe : warning LNK4088: image being generated due to /FORCE option; image may not run
Run test-fpga.exe to execute the test.
C:\intelFPGA_lite\17.1\hls\examples\counter>test-fpga.exe
PASSED
C:\intelFPGA_lite\17.1\hls\examples\counter>The contents of verification are:
Code:
\---verification
| compile.cmd
| modelsim.ini
| tb.qsys
| tb.sopcinfo
| transcript.log
|
\---tb
| tb.cmp
| tb.csv
| tb.html
| tb.spd
| tb_generation.rpt
|
\---simulation
| tb.sip
| tb.v
|
+---aldec
| rivierapro_setup.tcl
|
+---cadence
| | cds.lib
| | hdl.var
| | ncsim_setup.sh
| |
| \---cds_libs
| clock_reset_inst.cds.lib
| component_dpi_controller_count_inst.cds.lib
| concatenate_component_done_inst.cds.lib
| count_component_dpi_controller_bind_conduit_fanout_inst.cds.lib
| count_inst.cds.lib
| count_internal_inst.cds.lib
| irq_mapper.cds.lib
| main_dpi_controller_inst.cds.lib
| split_component_start_inst.cds.lib
|
+---mentor
| | msim_compile.tcl
| | msim_run.tcl
| | msim_setup.tcl
| |
| \---libraries
| | _info
| |
| +---clock_reset_inst
| | | _info
| | | _lib.qdb
| | | _lib1_0.qdb
| | | _lib1_0.qpg
| | | _lib1_0.qtl
| | | _vmake
| | |
| | \---_dpi
| | dpi.tfdb
| |
| +---component_dpi_controller_count_inst
| | | _info
| | | _lib.qdb
| | | _lib1_0.qdb
| | | _lib1_0.qpg
| | | _lib1_0.qtl
| | | _vmake
| | |
| | \---_dpi
| | dpi.tfdb
| |
| +---concatenate_component_done_inst
| | _info
| | _lib.qdb
| | _lib1_0.qdb
| | _lib1_0.qpg
| | _lib1_0.qtl
| | _vmake
| |
| +---count_component_dpi_controller_bind_conduit_fanout_inst
| | _info
| | _lib.qdb
| | _lib1_0.qdb
| | _lib1_0.qpg
| | _lib1_0.qtl
| | _vmake
| |
| +---count_inst
| | _info
| | _lib.qdb
| | _lib1_0.qdb
| | _lib1_0.qpg
| | _lib1_0.qtl
| | _vmake
| |
| +---count_internal_inst
| | _info
| | _lib.qdb
| | _lib1_0.qdb
| | _lib1_0.qpg
| | _lib1_0.qtl
| | _vmake
| |
| +---irq_mapper
| | _info
| | _lib.qdb
| | _lib1_0.qdb
| | _lib1_0.qpg
| | _lib1_0.qtl
| | _vmake
| |
| +---main_dpi_controller_inst
| | | _info
| | | _lib.qdb
| | | _lib1_0.qdb
| | | _lib1_0.qpg
| | | _lib1_0.qtl
| | | _vmake
| | |
| | \---_dpi
| | dpi.tfdb
| |
| +---split_component_start_inst
| | _info
| | _lib.qdb
| | _lib1_0.qdb
| | _lib1_0.qpg
| | _lib1_0.qtl
| | _vmake
| |
| \---work
| _info
| _lib.qdb
| _lib1_0.qdb
| _lib1_0.qpg
| _lib1_0.qtl
| _vmake
|
+---submodules
| acl_data_fifo.v
| acl_dspba_buffer.v
| acl_dspba_valid_fifo_counter.v
| acl_enable_sink.v
| acl_fanout_pipeline.sv
| acl_fifo.v
| acl_high_speed_fifo.sv
| acl_lfsr.sv
| acl_ll_fifo.v
| acl_ll_ram_fifo.v
| acl_low_latency_fifo.sv
| acl_pipeline.v
| acl_pop.v
| acl_push.v
| acl_reset_handler.sv
| acl_reset_wire.v
| acl_staging_reg.v
| acl_std_synchronizer_nocut.v
| acl_tessellated_incr_decr_threshold.sv
| acl_tessellated_incr_lookahead.sv
| acl_token_fifo_counter.v
| acl_valid_fifo_counter.v
| acl_zero_latency_fifo.sv
| bb_count_B0_runOnce.vhd
| bb_count_B0_runOnce_stall_region.vhd
| bb_count_B1_start.vhd
| bb_count_B1_start_stall_region.vhd
| count_B0_runOnce_branch.vhd
| count_B0_runOnce_merge.vhd
| count_B0_runOnce_merge_reg.vhd
| count_B1_start_branch.vhd
| count_B1_start_merge.vhd
| count_B1_start_merge_reg.vhd
| count_function.vhd
| count_function_wrapper.vhd
| count_internal.v
| dspba_library.vhd
| dspba_library_package.vhd
| hld_fifo.sv
| hld_fifo_zero_width.sv
| hls_sim_clock_reset.sv
| hls_sim_component_dpi_controller.sv
| hls_sim_main_dpi_controller.sv
| hls_sim_stream_sink_dpi_bfm.sv
| hls_sim_stream_source_dpi_bfm.sv
| i_acl_pipeline_keep_going_count6.vhd
| i_acl_pipeline_keep_going_count_sr.vhd
| i_acl_pipeline_keep_going_count_valid_fifo.vhd
| i_acl_pop_i1_wt_limpop_count0.vhd
| i_acl_pop_i1_wt_limpop_count_reg.vhd
| i_acl_pop_i32_cnt_count_4ia_addr_0_pop3_count15.vhd
| i_acl_push_i1_notexitcond_count8.vhd
| i_acl_push_i1_wt_limpush_count2.vhd
| i_acl_push_i1_wt_limpush_count_reg.vhd
| i_acl_push_i32_cnt_count_4ia_addr_0_push3_count17.vhd
| i_acl_sfc_exit_c0_wt_entry_count_c0_exit_count10.vhd
| i_acl_sfc_exit_c1_wt_entry_count_c1_exit_count19.vhd
| i_iord_bl_do_unnamed_count1_count12.vhd
| i_iowr_bl_return_unnamed_count2_count21.vhd
| i_sfc_c0_wt_entry_count_c0_enter_count.vhd
| i_sfc_c1_wt_entry_count_c1_enter_count.vhd
| i_sfc_logic_c0_wt_entry_count_c0_enter_count4.vhd
| i_sfc_logic_c1_wt_entry_count_c1_enter_count13.vhd
| st_top.v
| tb_concatenate_component_done_inst.sv
| tb_count_component_dpi_controller_bind_conduit_fanout_inst.sv
| tb_count_inst.v
| tb_irq_mapper.sv
| tb_split_component_start_inst.sv
|
\---synopsys
\---vcsmx
synopsys_sim.setup
vcsmx_setup.shCan someone help me with step-by-step instructions on how to run simulation
