Can't use linux after configuring the FPGA !!
Hi , I have an arria 10 SoC devkit, i have the default GSRD on HPS that contains the default partial reconfiguration rbfs (core.rbf , periph.rbf) , when i try to configure the FPGA using Quartus...
View ArticleUnivercity program VWF simulation error
I try to simulate Generic parity detector example in the book Circuit Design with VHDL. (Velnei A. Pedroni). But, simulation waveform editor gives an error. My synthesis editor is Quartus 2 web...
View ArticleQuartus Prime Lite 17.1 Code Revisions
Hi I'm looking for a way to have Quartus save and restore a history of code revisions, like say I have a project and I enter the code on the date 03/01/18, and then the next day I actually revise that...
View Article** Error: C:/intelfpga/17.1/quartus/eda/sim_lib/mentor/twentynm_atoms_ncryp
Hello, Anyone know what i may be doing wrong or need to do in order to get past this simulation problem? ** Error: C:/intelfpga/17.1/quartus/eda/sim_lib/mentor/twentynm_atoms_ncrypt.v(38): in protected...
View ArticlemSGDMA Transmission Data Missing
I am trying to transfer data using the mSGDMA QSYS cores in Quartus 17 from on-chip memory on an Arria V FPGA to a buffer allocated in Windows through PCIe and Jungos Windriver. Typically, the core...
View ArticleSetting up PCIe Connection Cyclone V
Hello, I am trying to set up a Cyclone V FPGA so that I can configure the core image through a PCIe connection. As far as I understand it, I need to create a .periph.jic file to upload to the FPGA...
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Getting started with Intel HLS tools [newbie]
Hello, world! I am a student working on my thesis. I am in the stage of knowing my tools and Intel HLS compiler is one of them. I know some things about Verilog HDL and some basic use of ModelSim and...
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SPI Slave Timing Constraint Question
Hi, I have designed an spi slave component and am having problems working out the best/correct way of creating timing constraints for the interface. A quick description of my component: The input nss...
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Simulating Arria10 designs in Verilog - twentynm_atoms_ncrypt.v
Hello, At this point I have multiple qsys designs that are failing in the standalone Questasim Core simulator. I get an error when Questasim tries to elaborate the Qsys design with vsim command. I...
View ArticleNeed help on 1588 TOD clock configuration register Read/write.
Hi, I am working on 1588 TOD clock IP, I have used the default configurations while generating the Altera TOD IP. In simulation, After few nano seconds, I am writing random value in Seconds L, Seconds...
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Sof unsuccessful on a stratix 10 board
Hello all, I'm tying to program a small counter design on the stratix 10 board and was unsuccessful. Things are very new to me as I was moved from xil to altera.IMG-20180413-WA0003.jpg Attached Images...
View ArticleCyclone V GT development board ethernet
I am trying to use Ethernet in a project. I am using an open core listed below, https://opencores.org/project/ethmac/overview I have used this core on DE2-115 board, but now when I am using the same...
View ArticleInteracting with HPC II DDR3 Controller via Avalon-pipeline bridge
When we try to access the HPC II controller with own Avalon-MM Master through Avalon-MM pipeline bridge,the slave doesnt response as expected during sequential read issues.Controller can accept read...
View ArticleAccessing the Reset Manager on Arria 10
Accessing the Reset Manager on Arria 10 Hi, I am trying to port an AMP configuration from Arria V to Arria 10. Linux is running on the first core and trying to start some baremetal code on the second...
View ArticleDE10 Standard - Very bad latency
Just got a DE10 standard, made a few quick tests and found integrated Ethernet has a very high latency. I mean, 0.9 milliseconds latency with a local ping against an expected base of 0.3 ms, like any...
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Programmer: Add new CFI Flash Device doesn't work
Hi there, I wanted to add a custom Flash device in Programmer (which is listed as compatible). So I use right mouse click -> Edit -> Define CFI Flash Device and can't find my device in the list...
View ArticleTimequest constraints for a dynamically phase-shifted PLL
I've been trying to properly constrain a design that uses dynamic phase shifting of an instance of an altera_pll core that I created. I.e. to enable phase-shifting I checked the "enable access to...
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about the IP core legacy EPCS/EPCQx1 Flash Controller does not support...
:confused: I'm confused about this IP core, because it doesn't support my new FPGA cyclone 10LP. Can someone give me any advise? Attached Images 捕获.JPG (17.0 KB)
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Implicit MUX selector not drawn?
Hello, In MAX V handbook, there are numerous places where the trapezoidal sign for mux are without selector signal. The screenshots are from Fig. 2.5 and 2.6. I do not see clearly where the selector...
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Sinh Viên
Dạ em chào các anh chị. Em là sinh viên ngành Điện tử - viễn thông. Hiện em đang làm đồ án Hệ thống Nhúng với board De2, đề tài của em là MẠCH ĐẾM SẢN PHẨM bằng xung clock, khi ấn key có xung clock...
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