From the release 13.0 of Quartus2, BFM in VHDL are supported.
Before 13.0, BFM were only supported in Verilog and there was a testbench example in System Verilog found in "Avalon Verification IP Suite Design Example" (ug_avalon_verification.zip) that worked fine.
Now I'm trying to adapt that example in a VHDL-only simulation in order to use Modelsim Starter Edition and BFMs with my VHDL custom files.
I'm finding some troubles for 2 reasons:
1) VHDL BFM approach is not well documented
2) the differences in hierarchy between Verilog and VHDL.
In the Verilog example, the top file and the test_program file were correctly separated and in the test_program.sv with the define you could access every signal in every like this:
and then use with the dot notation
What is the best way to accomplish this in VHDL? Is there anyone who has already adapted that example?
Thank you very much
Luca
Before 13.0, BFM were only supported in Verilog and there was a testbench example in System Verilog found in "Avalon Verification IP Suite Design Example" (ug_avalon_verification.zip) that worked fine.
Now I'm trying to adapt that example in a VHDL-only simulation in order to use Modelsim Starter Edition and BFMs with my VHDL custom files.
I'm finding some troubles for 2 reasons:
1) VHDL BFM approach is not well documented
2) the differences in hierarchy between Verilog and VHDL.
In the Verilog example, the top file and the test_program file were correctly separated and in the test_program.sv with the define you could access every signal in every like this:
Code:
`define CLK tb.st_bfm_qsys_tutorial_inst_clk_bfmCode:
`CLK.clkThank you very much
Luca