Handle DMA Page address received at the FPGA end during DMA transfer
Scatter Gather DMA transfer of 461KB is initiated from the Host PC to the ARRIA2GX FPGA using Jungo Driver. During the transfer apart from the actual data sent as input data , extra data which looks...
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Quartis v13.0 installation problem
Hi All,Im trying to install Quartus v13.0.0.156 and I keep receiving the following error message: Processor I7, RAM 8G, OS: Windows 7, 32bit I have Quartus v12.1sp1 installed on this computer....
View ArticleWhat is the polarity of DCLK signal in EPCS16 ?
I am using Cyclone III EP3C25 FPGA in which I have designed an sopc system which has Altera SPI IP. I want to access EPCS16 flash using this SPI. For that, what polarity should I kept for the SCLK...
View ArticlePolarity of DCLK signal in EPCS16?
I am using Cyclone III EP3C25 FPGA in which I have designed an sopc system which has Altera SPI IP. I want to access EPCS16 flash using this SPI. For that, what polarity should I kept for the SCLK...
View Articlepci express enumeration problem
Hi, We are using a 12 port PCI Express switch to connect 8 PCI Express cards. We are using Windows 7. The problem is when we connect the fifth card, windows keeps on loading but never starts. The fifth...
View ArticleGeneral Interrupt Problem
Hi everyone In my nios ii software in the main function there is "Function A" and "Function B" and there is a "Function C" which execute when interrupt occur like bellow Quote: int main() { //Function...
View ArticleSlave BFM not responding
Alright guys. So I've got a custom IP Avalon MM Master and I'm trying to check that it is implementing the avalon interface correctly. I've got it set up in a simulation with a slave BFM but while the...
View ArticleHow to communicate with Nios using JTAG UART module.
Hi All, I'd like to communicate with a nios system using a JTAG uart module, but I don't know which functions and libraries I have to use in nios C-program.. I have designed a system to glow the LED's...
View ArticleDifference between alt_write_flash and...
Hi, I have read the chapter on writing to Flash in chapter 6-19 of the Nios II Software Developer's Handbook. I understand the problem of overwriting data due to erasing and writing a whole block...
View ArticleQuestion about Modelsim user defined radix
Hi, In Modelsim wave view window, is it possible to set the radix for separate bit(s) in the signal. For example: 0000000010101100 (binary radix), instead of showing '172' in decimal radix, I'd like to...
View Articleinterfacing custom hardware with device toplevel
Hello, I know its a beginner question and I am reading the handbook also. However I would really appreciate if anyone can direct me to any example or give me some suggestion regarding the following. I...
View ArticleCyclone V and PCIe PIPE interface
Hi, I'm trying to use the PIPE feature of a Cyclone V GX (I'm using Quartus 13.0). When I was using a Cyclone IV GX, the PIPE interface was available through the ALTGX IP Megawizard. This IP has...
View Articleproblem to download ELF file to DE-1 board
I'm trying to download an elf file to the DE-1 board as described in the book: "EMBEDDED SOPC DESIGN WITH NIOS II PROCESSOR AND VHDL EXAMPLES" from Pong P. Chu, page 203: "Load the .elf file to the...
View ArticleQuartus Notification Center
Hi, Has anybody tried the new V13.0 Notification Center (http://cloud.altera.com)? With this feature, you can check on the Quartus compiler status from anywhere connected to the Internet, and you can...
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SRAM IP that work on some builds, and some it doesn't!
Hello All! I'm having an issue implementing some VERY simple IP for an asynchronous SRAM chip (on digikey: http://www.digikey.com/product-detai...104-ND/1831380). It's really making me doubt myself....
View Articlestratix IV EP4SGX230 shemtic library for Altium
I want to altium designer altera stratix IV lib EP4SE230 780pin,Seek help! Thank you!
View ArticleBFM in VHDL - from Quartus2 13.0
From the release 13.0 of Quartus2, BFM in VHDL are supported. Before 13.0, BFM were only supported in Verilog and there was a testbench example in System Verilog found in "Avalon Verification IP Suite...
View ArticleParametrically sized localparam assignment
I would like to be able to assign an array of localparams with some kind of static function. For example I don't want to have to do this: Code: localparam SIZE = 3; typedef logic [31:0] bar_t;...
View Articlespecify device family for megafunctions in command line?
Is it possible to change device family while generating megafunctions in command line? Thanks!
View Article1.8V I/O for DDR Controller? (BeMicro SDK MDDR)
The BeMicro SDK designs come with a Microtronix MDDR controller evaluation core. They use the 1.8V I/O standard, which allows them to use the thresh pin on the bank as the CS pin of the DDR. Whenever I...
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