compiling a design that instantiate 4096 times the same module
Hi, I'm writing a vhdl top code that instantiates 4096 the same module (using vhdl generate statement). The module consists in a RAM, plus an adder and some other logic ... and 4096 of them saturates...
View ArticleCyclone IV GX Transceiver Nios MAC
I am using the Cyclone IV GX Transceiver Starter Board and Quartus 12.1. The Qsys or SOPC tools seem straight forward on implementing the FPGA portion. The Nios II EDS provides a starter template...
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QuartusII 13.0.0.156 installation fails at the end
Hi there, I'm having trouble installing Quartus II, after installation is nearly complete ti freeze and show the next error. QuartusIIinstallation fail.jpg and after clicking the only choice I get next...
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nios2-elf-objcopy: command not found in Cygwin Windows 7, Nios II 12.1
Hi, We have a bunch of existing scripts used to generate srecs, .sh files. The scripts have been running for many years so I feel that the work. I am in the process of converting our build environement...
View ArticleConfigurable LUTs in Altera FPGAs
Hi, I've used Xilinx CFGLUT5 primitive quite a lot. It allows runtime LUT reconfiguration. The documentation of CFGLUT5 is here on page 74. This is a feature that saves lots of logic in certain kinds...
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Address comparator
Hello, 1)I have written a verilog module which compares 4 addresses to check if any of them are equal. - I have used xnor to compare the address. So a value of 1 indicates that the addresses are equal....
View ArticleNon-positive replication multiplier inside concat
Hi,recently I am focusing on a MSK IQ demodulating. after synthesize with Q2.9.1 and Pro Synplify.9.6.2,there come the warnings as following: # ** Warning: (vsim-8607)...
View ArticleLoading .rbf file into EPCS16 for remote configuration of FPGA.
Hi, I have prepared a qsys design(Say in Quartus_project_A) for writing and reading bytes with EPCS16 using SPI protocol(I am using EP3C25F25C68 FPGA) and it is working properly. Now, I want to load...
View Article"HW_MUL_SUPPORT" in Nios2-Linux with MMU supported distribution
All, Can anyone please explain how enabling/disabling "HW_MUL_SUPPORT" in Nios2-Linux with MMU supported distribution works? I'm using embed multiplier supported SOPC system. When I tested...
View Articledisplay serial data
hello:D I am beginner in Modelsim and i have a problem in displaying serial data.:( i want to display serial data every 16 clks as a word.(like multi line data) how can i do this? thanks a lot.:)
View ArticleSequential output of FSM in Verilog
Hi, I did a little experiment in Verilog as I set up a simple FSM and generate sequential output using the following code: Code: always@(posedge clk) begin case(state) st5:begin...
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DM9000A problem with sending packets
Hi guys, I have a problem with my DM9000A project. My project is sending packets from FPGA to PC using only VHDL codes to program. Some parts I copied from internet. Then I used wireshark to calculate...
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JTAG design for cyclone iii ep3c5E144
Dear all, This is my first attempt to create a FPGA board. My board only uses JTAG (no AS) for programming. I have attached the schematic and board in the *.zip file. Would you please having a look for...
View ArticleQuartus v13.0, QSys possible bug in passing parameters
QSys from Quartus v13.0 on my PC does not pass any component parameters to the generated master Verilog file. Like if you instantiate a video sync generator component, you will not see any of its...
View ArticleNIOS beginner- interfacing with hardware module
Hello! I am an absolute beginner in NIOS and would really appreciate if someone can help me with some advice with the following: I have a working hardware module synthesized in FPGA. I actually need to...
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Marketing a 【EP4CE DEV board】?
My team and I designed and manufactured a Cyclone IV FPGA development Board BlackDiamond which already been sold to more than 7000 FPGA starters and engineers in china. The main specifics...
View ArticleNios II flash programmer error
Hello all, I'm trying to generate the flash program to my device [de2-115], I'm generating the web server demo and using Nios II IDE (NOT Eclipse). However, I'm getting the error says on 80% of the...
View ArticleConvert real to integer in parameter
Hello. I am trying to synthesize some Verilog modules that are parametrized using real numbers. The real numbers get converted to actual integer values that are used for the module configuration using...
View ArticleThe basis about library
I am always confused by the usage and definition of library. Although currenly it looks like it did not affect my FPGA design and development, but I am eager to have a clear understanding about them....
View ArticleFirst time CPLD use questions - internal pull up resistor and clocking with...
I've designed a video game controller using Altera Max 7000s and Quartus 2 using the BDF process. 1-Was I suppose to add a clock? I only have inputs and outputs and logic gates needed in the bdf file....
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