Altera Mailbox Core and multiprocessor communication
Hi I have successfully instantiate multiprocessor in my design and now i want to somehow send some message between the processors In the Altera embedded IP document there is an IP core called "Mailbox"...
View ArticleQuartus and Xilinx
Hello all, A while ago I had read somewhere something that looked like you could compile a xilinx project with Quartus and I see a lot of answers when someone working with ise: use Quartus. So my...
View ArticleChecking configuration bitstream integrity (Cyclone IV)
I believe the configuration bitstream contains checksums or similar which the target FPGA checks for errors or corruption. Are the details of this integrity checking published? I'd like to have a host...
View Articleblock exponent in FFT core
One question regarding the block exponent in FFT core. I have set up a 8192 sample FFT engine using the FFT ip core. Now, does the same source exponent apply to EACH of the output FFT values? As in,...
View ArticleInterfacing (low speed) ADC reference board to FGPA board
Hello to everyone, I am back with another ADC board related question. Since I have started figuring out which reference boards I have always had to do with products mounting FMC or HSMC connectors, so...
View Articletracking time for real time control algorithm ??
Hi, i am new in VHDL, and i want to know if there is time() function at library that i can record time through for real time control algorithm using vhdl in my ALTERA DE2_70?? thanks
View ArticleDoes the order of the timing constraints make a difference to the Fit?
To "fudge" a project for now (a release is coming up - RTL changes will be needed but not enough time), I have a load of set_max_delay constraints that will only apply to the fitter ( if { $current_exe...
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Nonresolved signal has multiple sources
Hi all, A homework task I got is to create a component which receives positive numbers and gives the output of A+B-C+D-E... Compiling the code yields one error: # ** Error: checkex4.vhd(103):...
View ArticleStratix IV M9K blocks usage through DSP Builder
Hi, I want to utilize the M9K blocks of Stratix IV FPGA in True Dual Port mode. Can anyone please let me know how to use them through the DSP Builder? Thanks, Suresh
View ArticleMAX 7000 Help
Hello, I am using the EPM7128S and all I am trying to do is make the pins high (5v) or low (0V), but I'm not having any luck. This is my first time using this chip. For example here is the code I am...
View Articleuclinux PIO device driver interrupt handler not execute
Hi, Thanks in advance for any help I can get. I have a NIOS2 w/MMU running uClinux v3.7. It's a DE2-115 development kit with Cyclone IV FPGA. I use the PIO megafunction to monitor input rising edge...
View ArticleSo simple it's stupid: RS232 Receive Module works in Modelsim, fails in DE2-115
Hi. So, I am using Quartus II 12.1 sp1 and a DE2-115 board. I am running the clk at 100 MHz; at the top level it goes through a PLL to generate the 100 MHz clk. At the top level I am putting the data...
View ArticlePCIe BFM
I'm trying to set up a Qsys design using the PCIe core on an Arria II GX, and running into some problems. First of all, half of the documentation my version of the IP Compiler for PCI Express User...
View Articlesignal tap error
i am getting the below error, how to resolve? Error: Port "pre_syn.bp.UI_PM_CNTROLER_VALID_SPI" does not exist in the interface of the partition "F1_PM_HANDLER:PM_HANDLER_INST", but another partition...
View ArticleMultiple pin error?
Seems like a dumb question, but its strange to me as I havent used this version of Quartice for a bit. I have a Web Edition. In trying to compile the EP3C55 I get 3 multiple pin error messages of the...
View ArticleDoes logarithm megafunction do well??
Hello Sir, I am using ALTFP_LOG megafunction in my application, so when i verify this ip core, i get abnormal results for particular integer values. If i give particular inputs of few numbers to...
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Trying to on led using the input from pir sensor
Hi guys im very new in VHDL and im trying to write a program as to turn on an LED from the GPIO_0 which i put a PIR sensor to it..the PIR sensor is directly connectted to GPIO_O(0).. so the problem is...
View ArticleAOC Build Directory
There is a known issue with 13.0 AOC compilation: When running AOC to compile an OpenCL program file within a directory that contains spaces somewhere in the name, you will get an invalid argument...
View ArticleIs my Cyclone 2 in self protection mode ?
Hi all I have a relatively simple application running on a Cyclone 2 EP2c8, where the FPGA is the master for high speed bidirectional communication signals to another module. During operation at my...
View ArticleAudio project - 2D speaker array and mic array
Hi, For my Thesis on Audio processing. I want to develop a test bed to demonstrate DSP logic's(e.g. starting will be from LMS and then moving to complex logics) in real time. The test bed will consist...
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