Hi all
I have a relatively simple application running on a Cyclone 2 EP2c8, where the FPGA is the master for high speed bidirectional communication signals to another module.
During operation at my customer, occasionally the FPGA goes into a state where it requires a reset to continue operation.
I believe this occurs when the output pin is driving too much current due to the other module driving against the FPGA (timing issue).
I was unable to find any documentation on the behavior of the FPGA in the case where the I/O current limits are exceeded.
My question is :
Does such internal protection circuitry exist which sends the FPGA to some fault mode, where it stays until a reset is generated.
If so, is it possible to modify the behavior to control the behavior (reset automatically after some time etc).
Regards,
Adrian
I have a relatively simple application running on a Cyclone 2 EP2c8, where the FPGA is the master for high speed bidirectional communication signals to another module.
During operation at my customer, occasionally the FPGA goes into a state where it requires a reset to continue operation.
I believe this occurs when the output pin is driving too much current due to the other module driving against the FPGA (timing issue).
I was unable to find any documentation on the behavior of the FPGA in the case where the I/O current limits are exceeded.
My question is :
Does such internal protection circuitry exist which sends the FPGA to some fault mode, where it stays until a reset is generated.
If so, is it possible to modify the behavior to control the behavior (reset automatically after some time etc).
Regards,
Adrian