Hi,
I did a little experiment in Verilog as I set up a simple FSM and generate sequential output using the following code:
If I remember correctly, in VHDL similar code (clocked PROCESS I guess) would raise 'TestSignal' one clock cycle after entering 'state=st5'; however in Verilog 'TestSignal' rises as soon as the state transits to 'st5'. If this is way it works, then what's the difference between using always@(posedge clk) and always@(state) for the above code? Any hint?
Thanks a lot.
I did a little experiment in Verilog as I set up a simple FSM and generate sequential output using the following code:
Code:
always@(posedge clk)
begin
case(state)
st5:begin
TestSignal <= 1;
end
default: TestSignal <= 0;
endcase
endThanks a lot.