Hi,
I'm writing a vhdl top code that instantiates 4096 the same module (using vhdl generate statement).
The module consists in a RAM, plus an adder and some other logic ... and 4096 of them saturates the biggest stratix V that Altera have ...
It takes about 6 hours compile time ...
I wonder if exist a standard compile and place route procedure to perform this kind of designs, like compiling the single module only one time and
then placing the block 4096 times ... I'm new to this kind of modular and repetitive designs so can someone explain me which is the usual way of proceeding ?
Using logiblocks or partitions or something else could help ?
Thanks a lot
franco
I'm writing a vhdl top code that instantiates 4096 the same module (using vhdl generate statement).
The module consists in a RAM, plus an adder and some other logic ... and 4096 of them saturates the biggest stratix V that Altera have ...
It takes about 6 hours compile time ...
I wonder if exist a standard compile and place route procedure to perform this kind of designs, like compiling the single module only one time and
then placing the block 4096 times ... I'm new to this kind of modular and repetitive designs so can someone explain me which is the usual way of proceeding ?
Using logiblocks or partitions or something else could help ?
Thanks a lot
franco