Hello,
I am having a problem with my implementation of the triple speed ethernet core (details below). The ethernet interface works well 99.9% of the time for both Tx and Rx packets. On the Tx interface I am seeing intermittent errors that show up as an FCS error. After some investigation I have discovered that the problem lies in the RGMII Tx interface. I have put the external PHY into loopback mode so that the Tx packets can be analysed. Looping the packets back to the TSE core Rx has shown that there is a FCS error flagged, and I can see that one or more bits in the bad packets have been corrupted (always a 1 where there should be a 0). This happens for some bit sequences more than others (seems to be worse if one RGMII line has a 1 for consecutive cycles followed by a 0).
Investigating the RGMII interface on the PCB I've used a 2GHz scope with an equally good probe and I can see that the tx_clk and the rgmii data is far from ideal from a slew rate perspective (compared to the RGMII output signals of the PHY which are much more square).
The IO standard I've used for the RGMII Tx signals (Tx_clk, Tx_control, RGMII_OUT[3..0]) is 3V3 LVTTL at 8mA drive strength, I am not sure that this is correct but cannot find a definitive answer.
When I attempt to change this to 3V3 LVCMOS I get a warning that this standard can only be driven up to 64MHz and the resulting build does not work on the Tx side at all.
I cannot find a reference that indicates the source impedance of the LVTTL outputs so I am not sure that the termination resistor (33R) that I currently have on the board is right either.
I have followed AN477 to generate suitable constraints for the RGMII interface. The configuration is 3COM mode (delay implemented by the PHY) so the data and clk are edge aligned on the Tx side.
Can you suggest a possible cause of the problem or fill in some of the unknowns that I've mentioned above? Details of my system are below, if you need any more info please let me know.
Many Thanks,
David
Details:
FPGA: Cyclone IV EP4CE75F23I8L
PHY : Texas Instruments DP83865
On the PCB the RGMII interface traces are 50 Ohms characteristic impedance and length matched.
There is a 33R termination placed near to the PHY (I have also tried 47R and this improved the slew rate slightly but still get corruption).
I am having a problem with my implementation of the triple speed ethernet core (details below). The ethernet interface works well 99.9% of the time for both Tx and Rx packets. On the Tx interface I am seeing intermittent errors that show up as an FCS error. After some investigation I have discovered that the problem lies in the RGMII Tx interface. I have put the external PHY into loopback mode so that the Tx packets can be analysed. Looping the packets back to the TSE core Rx has shown that there is a FCS error flagged, and I can see that one or more bits in the bad packets have been corrupted (always a 1 where there should be a 0). This happens for some bit sequences more than others (seems to be worse if one RGMII line has a 1 for consecutive cycles followed by a 0).
Investigating the RGMII interface on the PCB I've used a 2GHz scope with an equally good probe and I can see that the tx_clk and the rgmii data is far from ideal from a slew rate perspective (compared to the RGMII output signals of the PHY which are much more square).
The IO standard I've used for the RGMII Tx signals (Tx_clk, Tx_control, RGMII_OUT[3..0]) is 3V3 LVTTL at 8mA drive strength, I am not sure that this is correct but cannot find a definitive answer.
When I attempt to change this to 3V3 LVCMOS I get a warning that this standard can only be driven up to 64MHz and the resulting build does not work on the Tx side at all.
I cannot find a reference that indicates the source impedance of the LVTTL outputs so I am not sure that the termination resistor (33R) that I currently have on the board is right either.
I have followed AN477 to generate suitable constraints for the RGMII interface. The configuration is 3COM mode (delay implemented by the PHY) so the data and clk are edge aligned on the Tx side.
Can you suggest a possible cause of the problem or fill in some of the unknowns that I've mentioned above? Details of my system are below, if you need any more info please let me know.
Many Thanks,
David
Details:
FPGA: Cyclone IV EP4CE75F23I8L
PHY : Texas Instruments DP83865
On the PCB the RGMII interface traces are 50 Ohms characteristic impedance and length matched.
There is a 33R termination placed near to the PHY (I have also tried 47R and this improved the slew rate slightly but still get corruption).