Interfacing of Nios-II and Triple Speed Ethernet in Qsys in MII Mode
Hi, In our design we migrate communication to Ethernet port. We have Cyclone-IV (E) EP4CE55F484 FPGA with DP83848C Ethernet PHY. We try to interfacing Ethernet PHY with Nios-II. We are using Triple...
View ArticleHow to use PCI BFM from altera for my PCI testbench ?
Hi Guys, Is it possible for me using PCI Bus Function Model from Altera Megacore for my own PCI code for testing ? I wanna modify the variable name inside PCI BFM from altera for my testbench, does it...
View ArticleQuartus II Subscription License
If i buy a subscription license for the Quartus II V13.0 Software and a NIOS II license too. Can i use this license files with older Quartus Versions too? Because most of my designs use SOPC Builder....
View ArticleCyclone III starter kit, Flash memory controller
Hi everyone, I'm new using this device. I'm trying to make a flash memory controller for the 128p30b flash memory. I've made the controller, I can read the memory succesfully, but I can't write. I've...
View Articleconversion of filesfrom pof to AHDL
Hai, can i get AHDL/VHDL file from pof /sof file? is it possible ?
View ArticleDDR and DDR2 SDRAM High-Performance Controller User Guide: question
Could somebody please explain the following from page 4-16 of the DDR and DDR2 SDRAM High-Performance Controller User Guide: To map local_wdata and local_be to mem_dq and mem_dm, consider the following...
View ArticleFTDI FT2232H Sync FIFO + FPGA
Hi guys, I'm using Morph-IC II and i'm having problems establishing the usb-communication between my Cyclone 2 and the FTDI FT2232H. My objective is to send a start/reset signal from PC->FPGA, then...
View ArticleUSB Blaster, Cyclone III, PS question
For development work, I would like to use a USB Blaster to configure a Cyclone III device in Passive Serial mode. Most of the USB Blaster is powered from the USB's VBUS except the I/O pins that connect...
View ArticleTSE Core RGMII Tx data corruption
Hello, I am having a problem with my implementation of the triple speed ethernet core (details below). The ethernet interface works well 99.9% of the time for both Tx and Rx packets. On the Tx...
View ArticleHow to trigger the Reset signal
Hi, Because the FPGA development board is installed on a remote machine, I have no access to the physical buttons on board, is there any other way to raise the reset signal after downloading the...
View ArticleMeasuring the dynamic power consumption of my C program
Hi, I am using a Cyclone III board with NiOS EDS v12.0. I have an image processing algorithm and I would like to measure the power consumption of this algorithm during its execution. I see that the...
View ArticleHello! Can you help me with a two 4-bit vectors divider for fpga
What I need is a divider which has as operands two 4-bit vectors(bit_vector(3 downto 0) or std_logic_vector(3 downto 0)). I only have to display integer results without '.' and what's after. Please...
View ArticlePLL not working in Modelsim
Hello, I'm using Quartus 12.1. I created a SOPC system, and now I'm trying to simulate it. In the SOPC builder I get a warning message : "altpll_0: The module properties SIMULATION_MODEL_IN_VERILOG and...
View ArticleMax V output pin in a disconnected mode on logic 1
I'm using Max V dev kit for basic logic gate design. No clocking or anything. Logic part works fine. On logic 1 / high I would like the output pin to be floating / disconnected. Right now it provides...
View ArticleDE4 Simple Socket Server
Hello I am starting to develop applications for the DE4 (Witch i just received not to long ago) and i am trying to run the demonstration simple socket server program that came with the board. reading...
View ArticleMax V power - convert 5v to 1.8v and 3.3v
I'm looking for way to power Max V CPLD. I have have either +5v from game console or 3xAA (1.5v) battery. Max V needs 1.8v and I think 3.3v for programming. Does anyone know of such a DC to DC...
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discuss about using opencore can bus ip core and develop with nios ii
recently, i am working on can bus communication of fpga. i downlownded an ip core from opencore. i use the ip core through c8051 interface. it is bulit in the system like:can软核.jpg, i process the ip...
View ArticleQuartus commands executed while working with Quartus GUI
Dear all I would like to automate my work using the Quartus commands executed when i use the Quartus GUI For Example : Step 1: I will open the signal tap file using Quartus Step 2: I will change the...
View ArticleAvalon MM Clock Crossing bridge
Hi, I'm a newbie with Qsys, can help me to understand what is the function of Avalon Clock crossing bridge module? And also the pipeline bridge. What are thier benefits and how they works in system?
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