What I need is a divider which has as operands two 4-bit vectors(bit_vector(3 downto 0) or std_logic_vector(3 downto 0)).
I only have to display integer results without '.' and what's after.
Please give me some code. I am a rookie in this. I need it for a project at college.
I've only been studying VHDL for at most a couple of months and I don't know to much.
I only have to display integer results without '.' and what's after.
Please give me some code. I am a rookie in this. I need it for a project at college.
I've only been studying VHDL for at most a couple of months and I don't know to much.