Quantcast
Channel: Altera Forums
Browsing all 19390 articles
Browse latest View live
↧

how to use the GXB interfaces in stratixV?

hello everyone: The prbs signals of the transmission rate for 1G / sI just need to transmmit a PRBS signal of the rate for 2G bit / s through the GXB pins. I used ALTGX cores when I use stratix IV...

View Article


DDR2 uniPHY Controller on Stratix IV (EP4SGX230KF40C2N)

Hello everyone, I am trying to create a DDR2 uniPHY controller on my Stratix IV DE4, I am using a compilation of altera tutorials to find my way out, but unfortunately am still not able to do it. I am...

View Article


MSEL wrong configuration

Hello, I designed a board using a EP4CE22F17C6N and I made a wrong connection on MSEL. I put it on MSEL[2..0] 001 instead of MSEL[2..0] 010. Besides the high level is tied to VCCio e.g 3,3V instead of...

View Article

Relationship among Niosii, Avalon MM interface, DMA etc..

Hi, Please help me to clarify the relationship among these terms... 1. Suppose I want to move a batch of data from SDRAM to the registers or BRAMs on a custom module using Avalon MM fabric. Currently I...

View Article

Low Pin Count FPGA/CPLD for FIFO+bits

Hi I'm an RF engineer with experience of programming PCs, PICs, EPLDs etc. I did once do an FPGA many many moons ago. I can't get the selection tool to make much sense, so here is my spec: 1. data...

View Article


Image may be NSFW.
Clik here to view.

Type 'xxx' could not be resolved

hey i am running continually into the same problem. when i load an example say the simple socket server example. The first time everything is nice and no errors show up. then if i close nios2 IDE and...

View Article

7 bit in 2 seven segments

hi guys i'm having a bit of a problem trying to figure out how to represent binary numbers up to 99 in 2 seven segments. i have my decoder code Code: library ieee; use ieee.std_logic_1164.all; entity...

View Article

Why I run tcl but it does't work?

I run the tcl script and it is executed,but it didn't change anything,the pin didn't set as i want? Cound you give any help?:(

View Article


Forlinx OK6410-A Board

I bought a OK6410-A from Forlinx, but as I input codes as per the instruction of latest files, the display content on DNW is as followings: Or click Forlinxtest to test WIFI, input password to click...

View Article


Image may be NSFW.
Clik here to view.

multiple clock problem

Hey! I am a beginner in VHDL programming and would like to ask a question to more advanced users. I am trying to write a simple shift register in order to control the stepper motor. Everything was ok...

View Article

HDL powerful editor.

HDL Editor: the HDL Powerful Editor Verilog, VHDL which editor to use better? Mention to the experience. I used Quartus editor, and there are always defects. Very much appreciate the IntelliSense...

View Article

Read float values from file stored on SD Card

Hello all, I have a matrix with float values which I will be saving in a file from Matlab. I have to copy this file to SD Card and read these values using NIOS 2 while running my program. What is the...

View Article

help with counter

im trying to learn to create counter that starts counting based on the input that from the expansion after i compile it it seems an error occur and i dont know how to solve it. help me guys.. this...

View Article


FIFO memory- code help

Hi! I need to make a FIFO memory in VHDL (XILINX) and I tryed a lot, but I have some problems and I can't understand what's wrong! :( I need to make PUSH and POP and to say when the memory is FULL or...

View Article

how to decrease compile time.

when a compile a project ,more than ten thousands lines. it used more than 3 hours. what i can do to avoid this. use good cpu? i used Xeon 3.4G 24G memory. optimize Quartus setting? but it not have...

View Article


unconnect port warning.

when a instance port is not connected, Quartus report a connectivty issue. how to avoid this.

View Article

Can Altera FPGA support DDR2 or DDR3 interchangable memory of PC?

I want my board to support DDR2 or DDR3 PC memory through standard memory slot. The FPGA should support most kinds of memory in stock. However when I tried to config DDR2 or DDR3 memory controller by...

View Article


Change Directory on SD Card

Is there a way to change the directory and read the wav files from sub-directories using the FatFileSystem functions available with SD Card Audio Player demo project on DE2-115 board? The functions are...

View Article

VHDL coding for quad mode shift register.

I am a beginner in vhdl coding. I need the vhdl coding and also the test bench coding for the quad mode shift register(SISO,SIPO,PIPO,PISO). Kindly pls provide the coding.... Thanks.....

View Article

set_false_path -from {ModA:ModA_inst|reg_src[144..244]} -to {ModB:ModB_inst|*} ?

I have a 2048 bit register that has a range of signals that need to be part of a false path. Instead of creating 100 lines like this: set_false_path -from {ModA:ModA_inst|reg_src[144]} -to...

View Article
Browsing all 19390 articles
Browse latest View live


<script src="https://jsc.adskeeper.com/r/s/rssing.com.1596347.js" async> </script>