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Low Pin Count FPGA/CPLD for FIFO+bits

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Hi

I'm an RF engineer with experience of programming PCs, PICs, EPLDs etc. I did once do an FPGA many many moons ago.

I can't get the selection tool to make much sense, so here is my spec:

1. data input to device is at 80Msps.. 3 lots plus external Clock.

2. data is all mashed up, so needs untangling, then FIFOing... ideally 24bits wide by 10, more if possible.

3. data then needs extracting on a parallel interface, 12 databits wide, plus a few control bits.

I need this for an IC production test board, we really don't care about chip cost (loadboard is >>£3k a pop).. but we are area limited. Also I want to avoid BGAs as they can't always be easily reworked and I don't want to be responsible for throwing away thousands of pounds of test boards.

Ideal package would be a TQFP, but beacuse of size constraints, as small as possible, maybe a TQFP 44.

any ideas?

mike

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