"Can't elaborate user hierarchy auto_fab_0" on adding signal_tap

Hi,

I have a design that uses some Altera RTL and some of my own RTL.

I am trying to add a few signals to Signal Tap, but on Analysis and Elaboration, I get this error:

"Error(13869): VHDL Binding Indication error at altera_mf_components.vhd(4895): design entity "altsyncram" does not contain generic "stratixiv_m144k_allow_dual_clocks" specified in associated component "
"Can't elaborate user hierarchy auto_fab_0"
"Error(19882): Automatic debug logic insertion has failed. "

If I remove all the signals from Signal Tap this error goes away.

I need to get around this error to debug on Signal Tap. Help?