Cyclone 10 GX transceiver tutorial
Hi, I have cyclone 10 GX development kit. I am looking for a step by step tutorial to make a loopback design with tranceivers. I am looking for a tutorial.
View ArticleFFT output spectrum generation
Hi all, I just have a simple question regarding to FFT output. I understand that the output of the real and imag signal have signed value, and these has to be divided by exponent value in order to get...
View ArticleExtraordinary long compilation time
Hello all. I am compiling a relatively simple OpenCL kernel for computing SHA-1 hashes. I've optimized and got everything working under the emulator and began building an AOCX file. That was over 12...
View ArticleQuartus ip-generate command: List of available components
Dear all, At the moment I am trying to port a project from the Arria X to the Arria V GZ. This project contains an PCIe interface and for performing simulations, a virtual root complex is necessary....
View ArticleProblem With Basically Everything
Greetings, The following forms a basis for my lack of understanding how Atlera has any market share whatsoever. I present the following points of fact regarding tool usability: Graphical Incompetency...
View ArticleParallel Flash Loader For MAX II .
Hi Everyone, I am using the Parallel flash loader for CPLD to configure an FPGA using an on board NOR flash. I have been able to generate the IP by following AN478 and AN386. I have instantiated a...
View ArticleDownload Link Missing: Gzip Compression OpenCL Design Example
Hey Community, Has anyone seen the download link for the Gzip Compression OpenCL Design Example? The landing page for this design alludes to having a download for Linux and Windows, but I don't see a...
View ArticleModelsim simulation error from HLS component.
Hi, I have abandoned the HLS component top module design in relation to the post I wrote below. Therefore, I decided to design top module with Verilog and manually instantiate the generated HLS IP. I...
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Encoder for dsd audio stream in SDIF-3 format, VHDL - help a newbie
Hello folks, I'm a newbie in VHDL programming. I'm trying to achieve SDIF-3 encoding from a dsd datastream coming off from an A-D conversion chip. The dsd stream from the chip features two independent...
View ArticleMemory Bandwidth using HMC and HBM technologies
I have read that HMC (Hybrid Memory cube) based memory technologies could produce memory bandwidths upto 75GB/s on Arria 10 devices. Which Arria 10 dev kit supports HMC based memory technology? I dont...
View ArticleTriple Speed Ethernet (1000-Mbps) : transmit Jumbo frames?
Hello all. I was working on a project with Triple-Speed Ethernet IP Core, and I'm having a bit of trouble understanding how to send jumbo frames. I built the system on Qsys with Triple Speed Ethernet...
View ArticleCompiling OpenCL kernel in Fedora 28
Hi, I have installed OpenCL SDK in my Fedora 28. But while trying to compile the kernel I am getting the following linking error, Quote: [sumanish@black vector_add]$ aoc -march=emulator -v -board=a10gx...
View ArticleDE5aNet-DDR4 opencl17.1 setup question
I"m trying to set up my DR5aNet DDR4 FPGA board. I installed OpenCL and Quartus Prime properly, following the manual. But the problem is I cannot compile a test project of fft1d.cl into fft1d.aocx. My...
View ArticleCan i just power the fpga part of the soc chip？
Hi，I plan to design a system with Arria10 SoC，Can I just power the FPGA part and leaving the HPS Part shut down? Thanks.
View ArticleThe L4 Watchdog Module Address Map is not exact in the hps.h
Hello, I would like to use header in my application using Altera Cyclone V. In the Cyclone V Hard Processor System Technical Reference Manual I can find this information about the Watchdog: L4 Watchdog...
View ArticleCache invalidation APIs and its usage in Altera Cyclone V SOC Linux
Hi all, We are conducting a feasibility study on our Altera Cyclone V SOC. We are having some streaming data receiving at FPGA at 300 Megabits per second. We have to transfer this data without any...
View Article"Can't elaborate user hierarchy auto_fab_0" on adding signal_tap
Hi, I have a design that uses some Altera RTL and some of my own RTL. I am trying to add a few signals to Signal Tap, but on Analysis and Elaboration, I get this error: "Error(13869): VHDL Binding...
View Articleddr3 RTL example of DE10 nano board
Hiii every one , I try to compile the example DDR3 RTL of DE10 nano board using quartus V16.0 but I get this warning : Warning (18236): Number of processors has not been specified which may cause...
View ArticleStratix II NIOS II devkit reference manual
Hello, I have old Nios Development Board Stratix II Edition (version 6XX-09900-0D), but I can't find reference manual for this version of the board. I found only this:...
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Getting Quartus to recognize a Recirculation Mux Synchronizer
Hi all, I'm attempting to perform a CDC of a Data bus that switches values with a Write Strobe using a "Recirculation Mux Synchronizer". In essence the Write Strobe is synchronized across the Async...
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