altera software download site maintenance
Anybody have any idea when altera software download site will be available again? we have developments undergoing and need to access some development tools. Thanks, Yong
View ArticleCyclone 10 GX transceiver tutorial
Hi, I have cyclone 10 GX development kit. I am looking for a step by step tutorial to make a loopback design with tranceivers. I am looking for a tutorial.
View ArticleFFT output spectrum generation
Hi all, I just have a simple question regarding to FFT output. I understand that the output of the real and imag signal have signed value, and these has to be divided by exponent value in order to get...
View ArticleExtraordinary long compilation time
Hello all. I am compiling a relatively simple OpenCL kernel for computing SHA-1 hashes. I've optimized and got everything working under the emulator and began building an AOCX file. That was over 12...
View ArticleQuartus ip-generate command: List of available components
Dear all, At the moment I am trying to port a project from the Arria X to the Arria V GZ. This project contains an PCIe interface and for performing simulations, a virtual root complex is necessary....
View ArticleProblem With Basically Everything
Greetings, The following forms a basis for my lack of understanding how Atlera has any market share whatsoever. I present the following points of fact regarding tool usability: Graphical Incompetency...
View ArticleParallel Flash Loader For MAX II .
Hi Everyone, I am using the Parallel flash loader for CPLD to configure an FPGA using an on board NOR flash. I have been able to generate the IP by following AN478 and AN386. I have instantiated a...
View ArticleDownload Link Missing: Gzip Compression OpenCL Design Example
Hey Community, Has anyone seen the download link for the Gzip Compression OpenCL Design Example? The landing page for this design alludes to having a download for Linux and Windows, but I don't see a...
View ArticleModelsim simulation error from HLS component.
Hi, I have abandoned the HLS component top module design in relation to the post I wrote below. Therefore, I decided to design top module with Verilog and manually instantiate the generated HLS IP. I...
View ArticleHow can I design RTL top component including sub HLS components?
Hi, I have created one component IP using intel HLS and I would like to create a top component code that five components is instanced. And each instance is timing parallel. Can I put component to top...
View ArticleModelSim-Altera show error on compilation while Quartus not.
Quartus compile this code without any errors. Code.sv Code: `timescale 1 ns/ 1 nsmodule test013_LITERAL (   input A,   input B,   output C );   struct{enum{IDLE,         SOME_STAGE_1}...
View ArticlePCIE to DDR4
I have follow PCIE DMA Access to External Memory reference design, I program sof file to FPGA, and reboot. I can see device through PCIE by "lspci | grep Altera", however, every time I try to transport...
View ArticleStratix V: 10Gb interface/transceiver noob questions
I am new to this family of the chips, and in general new to fast networking (however familiar with networking in general). I searched over the internet and scanned several documents, they have plenty...
View ArticleMax II Life cycle
Hi, We are using MAX II EPM240T100C3N device in our project and are considering using it in future projects. What is the Life cycle of this device? Best regards, Oren
View ArticleTerasic uboot
Hii I m working in a project using DE1-SOC board of terasic so i need to limit th linux partition of ddr3 sdram . does the terasic Uboot is open source so I can add the MEM=512M flag, or it's not open...
View ArticleClik here to view.
Problem with compiling Quartus project: Working project is not working any more
Hi all, I am facing a problem that is not going away in any way. The problem is when ever I compile my design it gives the following error: Can't place 37 pins with 2.5 V I/O standard because Fitter...
View ArticleMost Pin assignments are not visible in the Schematic (bdf) file
Hi all, This is my second thread of the day. I am sorry but I am frustrated as I am trying to solve these problem since many days. When I import .csv(pin assignment file) file into my project, although...
View ArticleClik here to view.
PLL of Cyclone V: 'reconfig_to_pll' bus description needed
Hi community, I'm working on a Project that has to be migrated from a Cyclone III to a Cyclone V FPGA. My problem is the PLL reconfiguration. Normally, the reconfiguration is processed by use of the...
View ArticleDE1-SOC hps ddr3 memory
Hii I m working in a project using DE1 soc board and i am trying to write data to hps ddr3 from FPGA .To do that i have to limit the memory used by linux ?I found that to limit the memory used by linux...
View Articlealtera software download site maintenance
Anybody have any idea when altera software download site will be available again? we have developments undergoing and need to access some development tools. Thanks, Yong
View Article