Cyclone IV transceiver kit (PCIe) FPGA board not detected on PCIE bus
Hi, I plug in my FPGA to my mother board. I'm running Ubuntu. I do lspci and I don't see my FPGA device. I only see these: 00:00.0 Host bridge: Intel Corporation Xeon E3-1200 v2/3rd Gen Core processor...
View ArticleThird party LDPC ip Core
Hello Any body using LDPC ip core on Altera platform which is optimum in terms of performance, resource and Latency. Altera own ip core having lot of limitation with compatible Encoder and Decoder- 1....
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about Arria 10 CvP Initialization
Dear Friends！ when I working on CvP confgures the FPGA fabric through the PCI Express® (PCIe) link ，I get the errors： ERROR：Timed out while waiting for CVP_CONFIG_READY == 0 ERROR : Timed out while...
View ArticleSystem Console connection problem with DE0-NANO-SOC kit
Hi, I am beginner with FPGA. I started with DE0-NANO-SOC kit and GHRD example supplied (DE0_NANO_SOC_GHRD) with the kit using Quartus 17.0 Lite edition. I am trying with System console to get hand on...
View ArticleIntel OpenCL SDK for Altera cyclone v does it requires licence
I brought DE10-Standard with cyclone v soc to test OpenCL applications, does i need licence to use intel OpenCL SDK
View Articleaocl program:Running reprogram from...
After typing aocl program /dev/acl0 vectorAdd.aocx system got hanged not display anything after this aocl program: Running reprogram from /home/root/opencl_arm32_rte/board/c5soc/arm32/bin
View ArticleCustom Instruction accessing SDRAM
Hello I am currently trying to update a memory location content inside SDRAM from a custom instruction(function called from nios ii). From what I understand, I need to use avalon memory mapped...
View ArticleNIOS II BSP: Problem building the project; No such file or directory
Hi all, I am trying to build a project. I manually added all the required files(copied) to the project after starting that project. But after every "Build Project" operation it is reporting: xyz.h: No...
View ArticleAbout THDB-ADA and other AD/DA Daughter cards
Hello all, According to the User's Guide of THDB-ADA (AD/DA converter), DC signals and low-frequency AC signals are not supported for AD or DA conversion operations. Since I need an AD/DA daughter card...
View ArticlePCI-E DMA for Arria 10
when I use arria 10 PCI-E ip in avalon ST with SRIOV mode,I found a problem. I can't found any example support PCI-E dma with avalon ST interface for Arria 10. altera offer example for SR-IOV,but the...
View ArticleCpld max v - i2s
hello everybody I'am a beginner at the VHDL programming. I use CPLD Max V (5M570ZF256C5N) in my internship and I have to write a program in VHDL. the program is selection between two audio sources via...
View Articlevector_add example - measuring the performance
Hello, I have executed the vector_add example on the DE10-Standard board and got the following output. It took 6.9ms kernel time to perform the floating point add operation on 1M elements. So, the...
View Articlevector_add example - Not using DSP blocks
Hello Everyone, I am trying to analyze the resource usage of opencl "vector_add.cl" example. aoc -c vector_add.cl -report +--------------------------------------------------------------------+ ;...
View ArticleAlternate solution for clGetPlatformIds
Hi, I have implemented a sample OpenCL program. In which kernel is consuming ~10 milli seconds and host API calls are consuming ~950 milli seconds. clGetPlatformIds() is consuming 840 milli seconds of...
View ArticleArria 10 Transceiver PHY latency estimation
Hi, I want to calculate/estimate the latency incurred in transmitting data from the Arria 10 Transceiver PHY IP. I looked into the user guide; it doesn' have any discussion on latency of the blocks, or...
View Articlealigned_alloc linker issues
I'm trying to share data between the ARM and the FPGA. I've made the F2SDRAM interface 256 bits wide. So, to make life easier I'd like to align the data to a 256 bit boundary. Figured I use the...
View ArticleCan generate POF file with OpenCore eval license
Hi. I try use in my design the SDI II core. I dont have license for it. I want compile my project and test SDI with JTAG connection. I use Arria 10 device and Quartus Prime Pro 17.1. I sucessed fit the...
View ArticleDHCP HostName definition in a socket server eth project
Hi all, I have developed a Nios FW with MicroC/OS-II and NicheStack TCP/IP, like the "simple socket server". Now I have enabled the DHCP option and the system runs correcty because the Router assign to...
View ArticleTo generate Pulse signals with Generic tri-state controller
Hi ! My task is to generate pulse and trigger signals using Quartus and NIOS Processor. I'm using Generic tri-state controller to communicate with registers in Quartus from NIOS to enable the signals....
View ArticleFitter is assigning pins according to the old pin plan
Hi, I have two FPGA designs for two different FPGAs(in Quartus). I did one project for one FPGA and then then copied the same project and modified it according to second FPGA. Now, I also changed the...
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