Having trouble constraining a bidirectional port in TimeQuest.
I've written a module to control the operation of an I2C bus where the SDA line is a bidirectional port. I've attempted to constrain it with these SDC commands: Code: set_output_delay -clock i2c_clk...
View ArticleUnable to constrain bidirectional port.
I have a module that is used to control the operation of an I2C bus. One of the outputs in the module is a bidirectional SDA line. I've attempted to constrain the design using the SDC commands: Code:...
View Articlegenerate the uboot.img
Hii , Can someone help me by telling me how to generate the "uboot.img", i generated the "preloader-mkpimage.bin" file but i don't know how to generate th "uboot .img" Im using DE1 soc board? the EDS...
View ArticleFAE Chat: Max10 ADC designs
Does anyone know of any working examples of ADC designs in a MAX10 device? Especially video using external memory and temp sense. Thanks Danny
View ArticleHLS Compiler support with cygwin/gcc
Is it possible to use HLS compiler (i++) with Gnu toolchain on Windows with cygwin? Also, why does keyword "HLS" yield zero results on the forum search? Is Intel trying to buy HLS?
View ArticleALTACCUMULATE not working in Quartus 17.1
I am migrating from Quartus 13.1 on a 32 bit Windows 7 to 17.1 on 64 bit Windows 10. My 1000 lines of AHDL code involving LVDS at 960MHz with a Nios II processor and tons of altera megafunctions have...
View ArticleWhere is the 322.265625 MHz clock on the Arria 10 SoC Dev Kit?
All, I'm testing the Intel Low Latency MAC 10G IP core with the 10GBASE-R Register Mode PHY and it requires a ref clock of 322.265625 MHz into a PLL (Figure 30, UG-20016 | 2018.05.16,...
View ArticleStratix 10 JTAG to Avalon Master Bridge Exception
I am attempting to use the JTAG to Avalon Memory Map Master Bridge IP core with a Stratix 10 Signal Integrity Kit but when I program the board with the System Console I get an exception saying that no...
View ArticleSPI by other descriptions
Hello all. I'm about to venture into my first SPI design for FPGA - and i'd like to scour the forums for information. When i search the forums for SPI the results are 0. What are the key words i should...
View ArticleMax 10: Lvds
I do like to have such a functionality in my design that could detect presence of data on LVDS lines and assert a flag. And in case no data is being received it can deassert the flag. I am using MAX-10...
View Article128 bit master to 32 bit slave
Hi , I am connecting a master whose data width is 128 bit. I am connecting it to a slave whose data width is 32 bit. Master output is Avalon interface When I trigger a data from the master, it is...
View Articlegenerate and compile the device trees
Hii every one, Im trying to migrate and let the DDR3_RTL project of DE10 Nano board works on the DE1-SOC. I change the pin and regenerate the preloader and uboot. so refering to this link...
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PISO reg issue
Hello there. I am trying to implement PISO register with this code (dout and tmp are regs) Code: always @(posedge sclk) begin if (cs == 0) begin dout <= tmp[15]; tmp...
View ArticleEthernetBlaster
Hi Does anyone have an EthernetBlaster that they no longer use and would like to sell? If so please reply to my post. Please note that I'm not after an EthernetBlaster II. Thanks
View ArticleError (209040): Can't access JTAG chain
Hello, I am trying to use the DE0-Nano board with Quartus Prime 18.0.0 (Linux) and I am experiencing problems when I try to load the .sof file to the board. The loading always fails and the only output...
View ArticleFIR Coefficient Reload Problmes
I've already posted an reply with a specific question regarding this problem into an old thread (https://www.alteraforum.com/forum/sh...ad.php?t=56082), but I think, I should start a new thread,...
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Soc/HPS based on DE10-Nano : how do I program a DPR and/or UART
Hello everyone, I am in a process of porting my application from a MAX10/DE10-Lite/NIOSII environment (https://github.com/pdp11gy/DEC-RL02-RL01-disk-emulator) to an SoC/HPC environment based on the...
View ArticleCurrent Measurement on Cyclone 10 GX Development Kit
Hello, I am studying how the Current Measurement was done on the Cyclone 10GX Development kit. I'm looking at the schematics page 38 and I don't understand what the Sense Pad V1 is and I don't see it...
View Articleproblem in installing quartus ii on ubuntu 16.04
HI I am intrying to install quartus ii on ubuntu 16.04 and getting the following error 11.0sp1_quartus_free_linux.sh: line 396: altera_installer/bin/altera_installer_gui: No such file or directory...
View ArticleHLS run Quartus compile FAILED.
My HLS quartus complies fails with following error, although synthesis is successfully. Info: Running Quartus Prime Synthesis Info: Version 17.1.0 Build 240 10/25/2017 SJ Pro Edition Info: Processing...
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