Pio write data error
Hi all, I am using IOWR_ALTERA_AVALON_PIOS macros to write data onto pios. But when I am writing the data onto 1 pins, all the other pins are assigned the same value at the same time. Does anyone know...
View ArticleEpf10k30ri240-4n, epf10k50ri240-4n
I need you expert opinion. I get this circuits from distributor, but I doubt in quality this product. On this product ink marking and other suspicious. In accordance with ADV0217, the laser marking...
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Kernel Panic programing fpga from Linux
Hello Community, I receive the following error when I want to program the fpga from Linux: Code: fpga_manager fpga0: writing fpga.rbf to Altera SOCFPGA FPGA Manager Unable to handle kernel NULL pointer...
View Articleverilog program
hello everyone, i am working on electro-chemical sensor. i am working for detection of cardiac troponin I in blood sample. I have to make a physical electronic device. for that motive, i think i have...
View Articleaocl list-devices : No devices attached for package:
When i run "aocl list-devices" command what i get is following output -bash-4.2$ aocl list-devices -------------------------------------------------------------------- Warning: No devices attached for...
View ArticleVerifying Configuration Memory after Programming
I'm working on an application for a high EMI environment and need to constantly verify the configuration of an FPGA to ensure that the circuit isn't being damaged/altered by the noise. I know I can do...
View ArticleTrouble using EPCS on Intel (Altera) DE10-standard
I'm using the DE-10 standard Intel FPGA. I'm trying to get a simple program that blinks a single LED to run when the FPGA is booted. From my understanding of the manual, the process involves converting...
View ArticleTCL console path initialization
I am trying to run commands in the Quartus 16.0 Tcl console window. Commands like quartus_map result in that the command name is invalid. I am running on Windows and have edited the PATH variable to...
View Article10GBase-R rx_ready not stable
Good afternoon, colleagues. I start 10GBase-R on Stratix V. The rx_ready status of the first 2-3 seconds is very unstable, then 0, then 1. What could be the reason? I suspect because of this link does...
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VHDL code error
Hello, I am trying to do Bit Error Rate Testor on my FPGA Altera Cyclone V board and SFP-HSMC. I am trying to send 3Gbps of data where as the maximum the transceiver or receiver can send or receive is...
View Articlemultiple kernel in a .cl file
I have a question about in appended single CL file case, 1、in followed CL file ,when only have clip_8b_kernel、ITransformOne_kernel、GetSSE_kernel and if put ITransformOne_kernel before GetSSE_kernel...
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8 MHz clock from 100 MHz
I am generating 8 MHz clock by scaling down the 100 MHz clock. The design I have implemented simulates well but when loaded on MAX-10 and observed using Signal Tap II logic analyzer the clock signal...
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Fft core generation stuck
Hi all, When I am using FFT core mega-wizard in Quartus 13.1, the toolbench stuck at this screen. And I have tried the solution of killing quartus-map in task manager, which this thing doesn't exist in...
View Articlecan't see enough FMAX
hello I create one FPGA project with CycloneV( 5CGXFC9E6F35C7 ). it has 80 pairs of LVDS inputs as DDRIO input. when I compile the project, it says FMAX is 103MHz that is too slower than I expected. I...
View ArticleUsing SPI core Stratix IV
Hello I want to use a Stratix IV dev kit to control an SPI device( it's a frequency generator board and it supports mini USB connection)! since the FPGA board only supports HSMC/PCI Express interfaces...
View ArticleStratix 10 Package Mechanical Drawings?
I've searched pretty thoroughly the Intel / Altera website and all the documentation the Stratix 10 and I can't seem to find the mechanical drawings for the packages. Has anyone run across them? I need...
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DDR3 hard memory controller usage issue
Hello all I have implemented a hard memory controller on the Altera Cylcone V SOC development board. The board calibrates successfully but when I write some thing to address '0' and try to read it...
View ArticleAltera Frame Reader Buffer Padding
I've been working on the Altera FrameReader IP core and have created a reference design for the Cyclone V SOC. I have a NIOS based software application that is using this design and displaying images...
View ArticleMAX10 initialization
Max10 devices don't have INIT_DONE pin to indicate initialization finished, How can I know the device goes into user mode?
View ArticleA question on Addressing of peripherals in Qsys
Hi, Background: I have generated a Qsys system. There is a 8 bit Pio in the design. After completion of the design, I assigned system address automatically. The situation is: system is assigning an...
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