can't see enough FMAX

hello

I create one FPGA project with CycloneV( 5CGXFC9E6F35C7 ).
it has 80 pairs of LVDS inputs as DDRIO input.

when I compile the project, it says FMAX is 103MHz that is too slower than I expected.
I need 300MHz.

I tried to compile each 8bits LVDS inputs independently.
then I found that some of them is 260MHz FMAX ( that still not enough by the way. )
the other hand, some other is 103MHz FMAX.

why LVDS input has different FMAX?
I mean this big difference.

do I miss something?

thank you.