OpenCL HostApp fails with acl_bind_buffer_to_device: Assertion `mem' failed
Hey, first some infos about the environment: Board: Nallatech 510T (2x Arria 10) Ubuntu 16.04. Quartus 17.1.0 Flashing the .aocx and compiling of the HostApp was successfull. Now when i start the...
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qsys avalon stream arbiter
I need module which has 2 Avalon-St sinks (data in) and single Avalon-St source (data out) and simply redirects one of the sink to source. Is there an option to make qsys infer arbitration logic and...
View ArticleCL_FLUSH is acting as Blocking call.
Hi All, I'm using non-blocking data transfer in my program to transfer 4K resolution(3840x2160) frame data. If clEnqueueWriteBuffer is blocking(CL_TRUE), it is consuming close to 3.5 millisec and if...
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Recovery timing violation
Hi all, I have a design with major recovery timing violation (among others). The design wasn't written by me, I'm only editing it, so I'm not fully aware of everything inside it. There's a photo in the...
View ArticleQUARTUS Software
Hello, I need to install the Quartus software on a production computer, to program boards. I am not currently registered on the website, and it seems registration on the website is not allowed right...
View ArticleA Beginner
Hi all, I am a beginner, with little knowledge of programming I want direction and guidance
View ArticleVHDL Code for a Mealy machine with two inputs and one output.
Hi guys, I'm new here. What would be the VDHL code for this Mealy machine? Thanks A sequential circuit with two Dflip-flops Aand B, two inputs, xand y; and one output z specified by the following...
View ArticleAltera Forum Migrates - existing email addresses
In the Altera Forum Migrates July 30th email sent it states :- "Top Altera Forum participants (those with a Pupil, Scholar, Teacher or Guru reputation) who have used the Altera Forum in the last 12...
View ArticleUnattended Install for Altera 13.1
I am trying to install Quartus II, ModelSim, SoCED and DSP Builder unattended with everything licensed with local license file. How do I do it. Thanks for your help. Cal
View ArticleMAX 10 SC and RAM blocks
In our design some RAM blocks are being inferred from our VHDL (no altera IP is being used). When targeting the device 10M16SCU169A7G and trying to compile the following error occurs: Error (16021):...
View ArticleMux for INOUT ports
Hey guys I'm trying to exchange 2 pairs of INOUT signals, but without much sucess so far. I have two PS/2 controlers and I would like to exchange the PS2(1) to PS2(2) signals and at same time PS2(2) to...
View Articleout_of_context mode equivalent in quartus tool
Hi Forum, I am a beginner in using quartus tool. I have a question regarding I/O buffer insertion in quartus. Earlier I used Vivado tool for synthesizing my design and I used out of context mode in...
View ArticleArria 10 SoC Development Kit - The function of FAHBP16 on Page 36
I am using Arria 10 SoC Development Kit (10AS066N3F40E2SG). And try to use the FMC A port for connecting an extra testing board. In the schematic (a10_soc_devkit_03_31_2016), some ports connect...
View ArticleHow to program EPCQ with .jic file on Altera C5EFP board?
I use C5EFP board, https://www.altera.com/products/boar...clone-v-e.html I program the EPCQ with jic file, get Error (209025): Can't recognize silicon ID for device 1 when it load 87%, but I can load...
View ArticleGenerated PCIe Gen3x8 example design for stratix 10 s1 board with "Enable DMA" ?
Hello all, In order to test and see the "HardIP for PCIe for stratix 10" IP component. I generated the example design from platform designer by configuring PCIe express IP with "Enable DMA option" and...
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LVDS Interface between two FPGA boards: Xilinx and Altera
Hi, I am making one-way communication between Cyclone V FPGA Board and Xilinx Kintex custom board. *Cyclone V FPGA Board: I/O standard = LVDS *Xilinx Kintex custom board: I/O standard =LVDS and LVDS_25...
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Xilinix to Quartus "Library Conversion"
Hi all, I have a library written by one of my ex-colleague for Xilinix ISE, It basically converts ML algorithms to HLS, Now I want to convert this library for Altera Fpga. I have used Altera...
View ArticleUnrolling and used RAMs
Hello, I'm trying to understand the relationship between channels, unrolls and used RAM (M20K) For this purpose, I've created this simple program composed of three kernels: - the first inject data into...
View Articlemem_fence() not working for channels
Hi all, I am testing the function of the feed-forward model(ping-pong buffer) mentioned in the programming guide. And I found the mem_fence function is not working. Here's the code I used for testing:...
View Articleconnect FPFA TO Internet using wifi adapter
I need help please ,How can I connect my board DE1-Soc FPGA to internet I have Wifi adapter RT5370 Wireless Adapter
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