DDR3 hard memory controller usage issue

Hello all I have implemented a hard memory controller on the Altera Cylcone V SOC development board.
The board calibrates successfully but when I write some thing to address '0' and try to read it back, I only see zeros. Read data valid does go high though.
I have attached signal tap screen caps. The first shows the write and read operation. The second shows read data valid going high but no valid data on readdata.

I have simulated the full design and it works correctly.

Any suggestions?

Thanks!

Attached Images

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