I am generating 8 MHz clock by scaling down the 100 MHz clock. The design I have implemented simulates well but when loaded on MAX-10 and observed using Signal Tap II logic analyzer the clock signal behaves completely different. Its period and duty cycle varies across the waveform.<br><img src="https://alteraforum.com/forum/attachment.php?attachmentid=15822&stc=1" attachmentid="15822" alt="Simulation" id="vbattach_15822" class="previewthumb"><br><img src="https://alteraforum.com/forum/attachment.php?attachmentid=15823&stc=1" attachmentid="15823" alt="As observed on Logic Analyzer" id="vbattach_15823" class="previewthumb"> Any guess why its behaves like this?
The design is based on a counter in verilog:
The design is based on a counter in verilog:
Code:
always @ (clk)
begin
if (clk_counter < 5'b01011)
begin
clk_counter <= clk_counter + 5'b00001;
end
else if (clk_counter == 5'b01011)
begin
SCLK <= 1'b1;
clk_counter <= clk_counter + 5'b00001;
end
else if ((clk_counter > 5'b01011) && (clk_counter < 5'b11001))
begin
clk_counter <= clk_counter + 5'b00001;
end
else if (clk_counter >= 5'b11001)
begin
SCLK <= 1'b0;
clk_counter <= 5'b00000;
end
end