I have a module that is used to control the operation of an I2C bus. One of the outputs in the module is a bidirectional SDA line. I've attempted to constrain the design using the SDC commands:
where i2c_clk is created with:
CLOCK_50 is a 50MHz input clock and {i2c:i2c_inst|i2c_clk} comes from the fact that my design instantiates the i2c module in a top level module.
The output delay seems to work fine. However, I'm getting errors associated with the input delay: "Warning (332174): Ignored filter at lab03.sdc(22): FGPA_I2C_SDAT could not be matched with a port" and "Warning (332049): Ignored set_input_delay at lab03.sdc(22): Argument <targets> is an empty collection". I thought this may have been an issue because I am specifying both input and output delays on the same port, but when I comment out the output delays I get the same error. Additionally, when I run TimeQuest to see the unconstrained input ports, it gives "FPGA_I2C_SDAT" (i.e. exactly the same as input I'm trying to constrain).
I noticed in Ryan Scoville's TimeQuest User Guide on page 114 that internal clocks should not be used to constrain IO ports. However, if I try it with a virtual clock of the same frequency I get the same error.
If any of this is unclear let me know and I'll clarify/post more code. Thanks in advance.
Code:
set_output_delay -clock i2c_clk -min 0.0 [get_ports {FPGA_I2C_SDAT}]
set_output_delay -clock i2c_clk -max 0.0 [get_ports {FPGA_I2C_SDAT}]
set_input_delay -clock i2c_clk -max 0.0 [get_ports {FGPA_I2C_SDAT}]
set_input_delay -clock i2c_clk -min 0.0 [get_ports {FGPA_I2C_SDAT}]Code:
create_generated_clock -source [get_ports CLOCK_50] -divide_by 126 -name i2c_clk [get_nodes {i2c:i2c_inst|i2c_clk}]The output delay seems to work fine. However, I'm getting errors associated with the input delay: "Warning (332174): Ignored filter at lab03.sdc(22): FGPA_I2C_SDAT could not be matched with a port" and "Warning (332049): Ignored set_input_delay at lab03.sdc(22): Argument <targets> is an empty collection". I thought this may have been an issue because I am specifying both input and output delays on the same port, but when I comment out the output delays I get the same error. Additionally, when I run TimeQuest to see the unconstrained input ports, it gives "FPGA_I2C_SDAT" (i.e. exactly the same as input I'm trying to constrain).
I noticed in Ryan Scoville's TimeQuest User Guide on page 114 that internal clocks should not be used to constrain IO ports. However, if I try it with a virtual clock of the same frequency I get the same error.
If any of this is unclear let me know and I'll clarify/post more code. Thanks in advance.