Hello there.
I am trying to implement PISO register with this code (dout and tmp are regs)
[15:0] tmp loaded elsewhere. So i need to convert parallel tmp in serial dout. During sim I saw that pic related: dout become tmp on second cycle, why?
Well, seems like i created two regs and they sequentially loaded (on first clk tmp, on second it is given to dout) but how to make them work together? I cannot name tmp "wire", gtkwave give error. Please, help me
I am trying to implement PISO register with this code (dout and tmp are regs)
Code:
always @(posedge sclk)
begin
if (cs == 0)
begin
dout <= tmp[15];
tmp <= { tmp [14:0], 1'b0 };
end
endWell, seems like i created two regs and they sequentially loaded (on first clk tmp, on second it is given to dout) but how to make them work together? I cannot name tmp "wire", gtkwave give error. Please, help me