SignalTap breaks my design

I'm using the DE2-115 development kit. It contains a Cylcone IV FPGA and I am interfacing that to the on board ISP1362 USB Driver (device mode only). My design asks the ISP1362 for it's chip ID. According to my external logic analyzer, 20 ns after I toggle the Read and Chip Select lines the ISP1362 will drive the bus. If the design is broken the ISP1362 drives the bus to 0, if it is working it drives it to 3630h. Again, working or broken the chip drives the bus at 20 ns after I toggle the read I/O. This is repeatable. The datasheet says it will take 22 ns to drive the bus to a valid value. My code toggles the I/O in the exact same way regardless if the chip responds correctly or not. I've measured the timing parameters and logic levels.

So, what breaks the design? In SignalTap if I set the sample depth to 8k the design works and I read 3630h. If I set the depth to 64k I read 0000h.

I understand that signaltap modifies the overall design, but does not (should not?) modify my code and thus does not modify my behavioral. I've constrained every signal in my design to 20 ns. (CLK is 50 MHz). I've used the generic I/O location/voltage level/constraint file. I've constrained the I/O to 20 ns as well. I've optimized the project for speed. I do not have any timequest timing violations and fmax in worst case scenario is 65 MHz (or so).

Where should I look to debug this problem?

I appreciate any questions, comments, concerns.

Attached Images

• signaltap8k.jpg (38.9 KB)
• signaltap64k.jpg (38.6 KB)