NIOS Software appears to restart
I built a first generation "larger than life" version of a product using an EP4CGX75 FPGA, and got my system and software running. I now have an ultra-miniature version of this using an EP4CGX15 part....
View Articlehow to find mac address of DE2 board
Hi guys, I got a project of sending packets from FPGA to PC via DM9000A using VHDL code, and i need the MAC address of the board but i dont know how to find it. Plz help me. Thanks
View ArticleDDR2 SDRAM Controller with ALTMEMPHY signals
Hello, I am using the DDR2 SDRAM Controller with ALTMEMPHY ip core. I received a reference design that I am basing my design from. What is the external_connection signal? In the reference design it is...
View ArticleURGENT URGENT URGEEEENNNNNT: My DE2 borad BURNED and i don't know what to...
Hi guys, I'm only couple of weeks away from my graduation day and i'm working on a project to control multi-cars elevator system using NIOS II which was working just fine today untill............
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SignalTap breaks my design
I'm using the DE2-115 development kit. It contains a Cylcone IV FPGA and I am interfacing that to the on board ISP1362 USB Driver (device mode only). My design asks the ISP1362 for it's chip ID....
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Altera Stratix IV GX FPGA fundamental communication DE4(EP4SGX230C2)
Hi everybody, I am a newbie trying to figure out how to implement a fundamental communication between PC and the FPGA board using PCIe. Basically we have all the PHY data processing ready in the FPGA...
View Articlex2 PCIE Design
Hi, I would like to design a x2 PCIE Gen 2.0 root port. In the system settings in Avalon MM Hard IP for PCIE, the option for number of lane is only x1 and x4. It says that if I will design x2 lane, I...
View ArticleUrgent help on licensing
Hello there, I'm a newbie to altera and this licensing issue has really slowed my research. I have a DE III board (Stratix III), given to me by my university to carry out my research. I made some...
View ArticleProblems with OpenCL SDK 13.0 on Windows 7
hai all. i installed Quartus II 32-bit Shell and Altera SDK for OpenCL C:\Users\Udaya>quartus_sh --version Quartus II 32-bit Shell Version 13.0.0 Build 156 04/24/2013 SJ Full Version Copyright (C)...
View ArticleCyclone IV no JTAG access after PS configuration
Hi I use passive serial configuration for a EP4CE10F17C8 device (a DSP controls the nSTATUS, nCONFIG, DCLK and DATA0 ports of the FPGA) After configuration the FPGA releases CONF_DONE as it should, and...
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PCIe Endpoint requester
Hi all, What i want to do here is just a simple thing and i'd like to have your advices before to start. I want to make a point to point PCIe communication between an EndPoint and a Root. The Endpoint...
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sscanf and sprintf
1. Version 13.0 vs 12.1sp1 Recently we try the version 13.0 with our working software in 12.1sp1 but we have a surprise it was not working properly. We have found why, it is because the compiler does...
View ArticleNIOSII Syntax on Quartus 13
I am having a problem verilog syntax NIOS suggest for exporting the signals into Quartus for version 13. In some cases it suggest to use '.bidir_port_to_and_from_the_sys_scl' and in some other cases it...
View ArticleUndefined reference to `OSStart´
Do anyone know how to overcome the error ¨undefined reference to `OSSstart´? I am using Eclipse to build the system. The error I believe is because micrium_uc_osii header files are not included...
View ArticlePCIe Hardip going from x1-to-x4 Error "transmit_pcs0" has illegal fan-out
Hi all, I have a design with a PCIe HardIP in Stratix IV, both RootP and EndP which work fine as Gen-1, X1. Now I am trying to upgrade and go for Gen-1, X4 while keeping everything the same (125Mhz...
View ArticleDSE Compiles wont use spare processors
Project file has the project set to use multiple processors when available. But when I run DSE each run seems to only want to run on a single core. I have a 6 core xeon running a two seed run, and 4 of...
View Articlenios processor memory
Is there any way in SOPC builder or Qsys to use a costume memory as main processor SRAM? In my build I can only use of on chip RAM or ROM. NIOS processor can not detect another type of memory as its...
View ArticleSynchronization Chains not detected
Hi there, I have clock domain crossing in my design. I use synchronization chains for metastability. In a part of my design I instantiate a custom made dual clock FIFO. After the flow is completed I...
View ArticleGate Level Netlist
Let's say that you have a hierarchical design with the Top Level file (call it topLevel.vhd) instantiating various modules such as modA.vhd, modB.vhd, modC.vhd, and so on. Is their a way to have...
View ArticleNios II has no sleep/idle/wfi instruction?
My software is event driven, the idle time is spent in a loop polling for new entries in a message queue, which get filled in by my ISRs. With other controllers, this is the perfect place for a sleep...
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