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ALTGX PIPE byte order alternates for each SKP ordered set received
IÂ’m working on a PCI Express Protocol Analyzer design which uses an Arria II GX (EP2AGX45DF29C5). An external probe creates copies of the x4 Host-to-Device (H2D) and x4 Device-to-Host (D2H) data which...
View Articlepin assignment for DE2 board
I need to assign pins for DE2 board. However, when I go to "assignments" in the toolbar, I couldn't find the "pin" selection. I couldn't bring out the pin assignment graph via assignment editor in the...
View ArticleError : object used but not declared
Hi, I just want to create a signal_copie_req out std_logic : entity test_connexions is port( signals ... signal_copie_req : out_std_logic; )... COMPONENT test_connexions PORT( signals ......
View ArticleRegisters in series - why clock time delays?
Hello people! Can someone please explain why is it that there is one clock delay to transport input to output when I have two registers (Flip Flops) in series? I mean the transport time form the input...
View ArticleWhere to find the Date Code on the device?
Where can I find the date code on the EPM7096 EPLD device? Can show a picture of the date code on the device will be good. Thanks!
View ArticleMigration Error from NIOS 11.2 to NIOS 12.1
After rebuilding my project after a long pause I discovered a building error in NIOS that seems to be related to the update from NIOS 11.2 to NIOS 12.1: Code: Description  Resource  Path...
View ArticleCyclone IV E JTAG inputs board pull-up to VCCA instead of VCCIO?
Shouldn't Cyclone IV E JTAG inputs be pulled up on the board to VCCIO (3.3V in our case) instead of VCCA (2.5V) as recommended in the pin connections guidelines? The device handbook says "all the JTAG...
View ArticleBGA practice devices needed
I'm looking to get some 'dummy' devices to help develop a reflow profile for BGA rework. The package I'm looking for is the 100 pin MBGA (EPM570M100C5N). Does anyone know if Altera sells dummy...
View Articleset false path between clocks
Hi there If I have clock domain crossing in my design, should I set all paths between the two clocks as false path ? I'm working on a design and got setup&hold violations on a path crossing between...
View ArticleCopy project and Archive project
Hello, When I copy a project, it took to 5 minutes but when I chose to archive it, it took only about 1 minute. So what's different between Copy project and Archive project? thanks!
View ArticleSystem Checks fail
Preperations: I followed the usual work flow: Generate Qsys system > Build Quartus Project > Use Programmer to write the hardware on the FPGA > Generate the BSP in NIOS > Run the program as...
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Debugging JTAG for cyclone III
Hi, I have just finished my very first FPGA board, with an EP3C5E144C8N programmed by JTAG (no AS). I have attached the design in *zip.files (actually it is the old circuit, I changed thing a bit but...
View Article1-Shift PRBS
Hello, I have reading a lot of posts that they are talking about shift registers, but always they are refered to a fix data, not to PRBS. What I would like to get is from a PRBS generator (can be the...
View ArticleM9K parity usgae
Folks, Is there any way to use the whole 9Kbit of each M9K in Cyclone III? My observation shows that Quartus compiler tool utilizes M9K as 8kbits blocks of memory. I intend to use the extra space for...
View ArticleCyclone V: PCIe x4 + XAUI.
Hello! I have 5CSXFC6D6F31C6. Can I used PCIe x4 and XAUI simultaneously?
View Articlecreate a vector waveform file
I am trying to set up the values for input signals at different time period. However, I simply couldn't bring out the "Arbitrary Value" window out --- only part of the window shows up with options to...
View ArticleNIOS: Simulating the JTAG UART
I would like to simulate the "Hello World" project. Is there a way to get the simulation model for the JTAT UART to simply display its data and NOT back up and cause processing to stop? Rod
View ArticleCan SFP or SFP + interface directly with stratix iv gx?
Can SFP or SFP+ interface directly with stratix iv gx gxb pin? and use fiber module of SFP/SFP+ to communication each other stably? thanks for your replies! :confused:
View ArticleEP4SGX70HF35C2 needs FAN?
what's max power consumes about the EP4SGX70HF35C2 ? and Need a Fan ? thanks!
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