Hi there
If I have clock domain crossing in my design, should I set all paths between the two clocks as false path ?
I'm working on a design and got setup&hold violations on a path crossing between the two domains. In time quest anaylzer I right-clicked the path and chose set false path between clocks. The SDC file was updated. I recompiled the project and got the same violation between the same nodes !
Am I missing something ?
How can I check if a constraint is ignored or not ? May be the false path constraint is ignored.
The two clocks are generated from different PLLs. They are completely unrelated, each of them is driven from a different oscillators. Please help, I got sick of this issue :mad:
If I have clock domain crossing in my design, should I set all paths between the two clocks as false path ?
I'm working on a design and got setup&hold violations on a path crossing between the two domains. In time quest anaylzer I right-clicked the path and chose set false path between clocks. The SDC file was updated. I recompiled the project and got the same violation between the same nodes !
Am I missing something ?
How can I check if a constraint is ignored or not ? May be the false path constraint is ignored.
The two clocks are generated from different PLLs. They are completely unrelated, each of them is driven from a different oscillators. Please help, I got sick of this issue :mad: