Cyclone IV no JTAG access after PS configuration

Hi
I use passive serial configuration for a EP4CE10F17C8 device (a DSP controls the nSTATUS, nCONFIG, DCLK and DATA0 ports of the FPGA)
After configuration the FPGA releases CONF_DONE as it should, and the user mode is correctly entered. The DSP releases nSTATUS, nCONFIG, DATA0 and DCLK,
these signals are tied to VCCIO by pull up resistors.


The problem is: After PS configuration there is no JTAG access any more by the USB blaster for signal tap debugging.
Error (209040): Can't access JTAG chain
Error (209012): Operation failed


If the hardware is in a "virgin" state, that means no configuration by the DSP takes place, JTAG access by the
USB blaster works fine.

This is what the Quartus JTAG Chain Debugger says:
1) The TAP controller can be reset or put into idle state (but this does not help)
2) If I run "Test JTAG Chain", usually the device cannot be identified (wrong or ambiguous ID, or sometimes even several devices are detected)


Is this a hidden feature of Cyclone IV E devices or a undocumented anti-tampering mechanism?
I always thought JTAG works independently of any other configuration schemes.
I assume some JTAG-related registers are overwritten or corrupted during PS configuration, but which ones, and how could this be avoided?

Is there any way to clear the device configuration in order to regain access using the Quartus JTAG Chain Debugger?

Any suggestions will be appreciated.

regards
peter