Hello
In my sdudy final project I use CPLD in order to make some operations.
I control the cpld via the computer parallel port.
Because the port is not bidirectional, but requires a time open it in any direction I have some problem.
When I do a reading or writing separately everything works ..
Because I think the CPLDvworks faster than the computer I get inconsistent results.
Attached code, if anyone has comments it really helps.
In the PC side I am using C language:
VHDL Code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Dvir is
port(
sig_in : in std_logic;
sig_buff : buffer std_logic;
clk : buffer std_logic;
data : inout std_logic_vector(7 downto 0);
testdata : out std_logic_vector(7 downto 0);
strobe : in std_logic; --active high
--resetn : in std_logic; --active low
ack : out std_logic; --active high
testLed : out std_logic
--est1 : out std_logic
);
end Dvir;
architecture Behave of Dvir is
signal inData :std_logic_vector(7 downto 0);
signal outData :std_logic_vector(7 downto 0);
signal intClk :std_logic;
signal intCnt :std_logic_vector(19 downto 0);
signal intFlag :std_logic;
begin --architecture
testLed <= intFlag;
testdata <=outData;
data<= outData when strobe='0' else (others =>'Z');
ack <= '0' when strobe='0' else '1';
d:process(strobe)
begin
if strobe='0' and strobe'event then --cpld write
outData<= not inData;
end if;
end process d;
wr:process(strobe)
begin
if strobe='1' and strobe'event then --cpld read
inData<= data;
end if;
end process wr;
end Behave;
Thanks!
In my sdudy final project I use CPLD in order to make some operations.
I control the cpld via the computer parallel port.
Because the port is not bidirectional, but requires a time open it in any direction I have some problem.
When I do a reading or writing separately everything works ..
Because I think the CPLDvworks faster than the computer I get inconsistent results.
Attached code, if anyone has comments it really helps.
In the PC side I am using C language:
VHDL Code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Dvir is
port(
sig_in : in std_logic;
sig_buff : buffer std_logic;
clk : buffer std_logic;
data : inout std_logic_vector(7 downto 0);
testdata : out std_logic_vector(7 downto 0);
strobe : in std_logic; --active high
--resetn : in std_logic; --active low
ack : out std_logic; --active high
testLed : out std_logic
--est1 : out std_logic
);
end Dvir;
architecture Behave of Dvir is
signal inData :std_logic_vector(7 downto 0);
signal outData :std_logic_vector(7 downto 0);
signal intClk :std_logic;
signal intCnt :std_logic_vector(19 downto 0);
signal intFlag :std_logic;
begin --architecture
testLed <= intFlag;
testdata <=outData;
data<= outData when strobe='0' else (others =>'Z');
ack <= '0' when strobe='0' else '1';
d:process(strobe)
begin
if strobe='0' and strobe'event then --cpld write
outData<= not inData;
end if;
end process d;
wr:process(strobe)
begin
if strobe='1' and strobe'event then --cpld read
inData<= data;
end if;
end process wr;
end Behave;
Thanks!